公开(公告)号：US12079086B2

公开(公告)日：2024-09-03

申请号：US17804936

申请日：2022-06-01

申请人： NXP B.V.

发明人： Steffen Mueller ,  Lucas Pieter Lodewijk van Dijk ,  Georg Olma ,  Joachim Josef Maria Kruecken

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/14 ,  G06F11/30 ,  H04L1/00 ,  H04L12/40 ,  H04L43/0823

CPC分类号： G06F11/142 ,  G06F11/0739 ,  G06F11/0793 ,  G06F11/3027 ,  H04L1/0006 ,  H04L12/40 ,  H04L43/0847 ,  H04L2012/40215

摘要： The disclosure relates to a transceiver device for communicating between a network protocol controller and a network bus, the transceiver device comprising: transceiver circuitry configured to transmit and receive data on the network bus using a first physical layer protocol; and monitoring circuitry configured to determine a measured property of the network bus, in which the transceiver device is configured to: determine whether the measured property indicates an error condition; and reconfigure the transceiver circuitry to transmit and receive data on the network bus using a second physical layer protocol in response to determining the error condition.

公开(公告)号：US20230367684A1

公开(公告)日：2023-11-16

申请号：US18249703

申请日：2021-07-29

申请人： INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.

发明人： Liang CUI

IPC分类号： G06F11/30 ,  G06F13/42

CPC分类号： G06F11/3027 ,  G06F13/4282

摘要： An ESPI-based method and device for enhancing server security, including: S100, a Complex Programmable Logic Device (CPLD) monitors packet formats and instructions on an Enhanced Serial Peripheral Interface (ESPI) bus; S200, when the CPLD monitors an abnormal firmware Flash read/write operation, the CPLD records operation-related records in a Flash which is mounted to the CPLD; S300, the CPLD lights a Light-Emitting Diode (LED) corresponding to a system error signal line or a LED corresponding to a Baseboard Management Controller (BMC) error signal line; S400, the CPLD determines whether to take over a CS0 signal or not; S500, when the CPLD determines to take over the CS0 signal, the CPLD requests to interact with a Platform Controller Hub (PCH) and warns of a system security issue.

公开(公告)号：US11735026B1

公开(公告)日：2023-08-22

申请号：US17590630

申请日：2022-02-01

申请人： C/HCA, Inc.

发明人： Christian Krayer ,  William Michael Gregg ,  Thomas Andrew Doyle ,  Paul Brient ,  Jim Najib Jirjis ,  Karl Bradley Kehler ,  Jonathan Perlin ,  Paul Martin Paslick ,  Edmund Jackson ,  Sarah Hume Buta ,  Erin S. Jospe ,  Umesh P. Phirke ,  Steven V. Manoukian ,  Vincent Doyle, III ,  Wesley Boles ,  Ravi S. Chari

IPC分类号： G08B21/18 ,  G06F11/30

CPC分类号： G08B21/182 ,  G06F11/3027

摘要： In some examples, systems, methods, and devices are described that generate contextual suggestions for patients. Generation of the contextual suggestions is triggered by certain events performed by a medical professional with respect to a patient (e.g., updating a patient record). The contextual suggestions are related to addressing health conditions of the patient and represent tasks or considerations which the medical professional should be made aware. The contextual suggestions are generated in a way that is considerate of patient context, medical professional context, and contexts of similar patients. The contextual suggestions can be presented to the medical professional for selection and execution.

公开(公告)号：US11704218B2

公开(公告)日：2023-07-18

申请号：US16852246

申请日：2020-04-17

申请人： CANON KABUSHIKI KAISHA

发明人： Hiroyoshi Ooshima ,  Tetsuo Uchiyama

IPC分类号： G06F11/32 ,  G06F11/30 ,  G11C11/4076 ,  G11C11/406

CPC分类号： G06F11/322 ,  G06F11/3027 ,  G06F11/3037 ,  G11C11/4076 ,  G11C11/40622

摘要： An information processing apparatus includes a detection unit and first and second classification units. The detection unit detects an event which causes a state of at least one bank constituting dynamic random access memory (DRAM) to transition. The first classification unit classifies the at least one bank state based on the detected event. The second classification unit classifies a DRAM state based on the at least one bank state. Statistical information that is based on the at least one bank or DRAM state is displayed with respect to a predetermined unit time. The at least one bank state and the DRAM state each includes at least one of the following: an operating state, in which data is being transferred, an inoperative state, in which data transfer is not possible due to a predetermined constraint, or a pause state, in which, although there is no constraint, data is not being transferred.

公开(公告)号：US20180329846A1

公开(公告)日：2018-11-15

申请号：US16045591

申请日：2018-07-25

申请人： Apple Inc.

发明人： Torrey H. Walker ,  Daniel C. Klingler ,  Balasubramanya Bhat

IPC分类号： G06F13/38 ,  G06F11/30 ,  G06F13/42 ,  G06F9/54

CPC分类号： G06F13/385 ,  G06F9/54 ,  G06F11/3027 ,  G06F11/3051 ,  G06F13/4282

摘要： A method for reconfiguring a bus device from a first configuration into a second configuration, wherein the second configuration is not visible to, and is not selectable by, an unauthorized host device that connects to the bus device through a peripheral port of the bus device is described. In the bus device, a received message transmitted by the authorized host device through the peripheral port of the bus device to which the authorized host device is connected is parsed and an instruction to reconfigure the bus device from the first configuration into the second configuration is detected. Responsive to detecting the instruction, a daemon signals reconfiguration of the bus device into the second configuration, and responsive to the daemon signaling, the bus device is reconfigured into the second configuration. Other embodiments are also described.

公开(公告)号：US10055322B2

公开(公告)日：2018-08-21

申请号：US15025565

申请日：2013-09-30

申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

发明人： Alex Gunnar Olson

IPC分类号： G06F11/00 ,  G06F11/30 ,  G06F11/16 ,  G06F11/22

CPC分类号： G06F11/3027 ,  G06F11/1625 ,  G06F11/221

摘要： A technique includes receiving a first signal from a first bus, and receiving a second signal from a second bus. The first and second buses are used for redundant communications. The technique includes interpreting the first and second signals to derive a bus data input signal for a controller based at least in part on detection of a predetermined bus fault.

公开(公告)号：US20180113779A1

公开(公告)日：2018-04-26

申请号：US15557402

申请日：2016-03-11

申请人： Protocol Insight, LLC

发明人： Anthony Peter Carosa ,  Ross Nelson

IPC分类号： G06F11/34 ,  G06F13/42 ,  G06F11/30

CPC分类号： G06F11/349 ,  G06F11/3027 ,  G06F11/364 ,  G06F11/3656 ,  G06F13/4282 ,  H04L29/06 ,  H04L43/18 ,  H04L43/50

摘要： An intelligent packet analyzer circuit is configured to capture traffic being communicated over a serial communications bus. The intelligent packet analyzer circuit is further configured to analyze the captured traffic to identify a type of transaction being communicated over the serial communications bus and to analyze the packets being communicated over the serial communications bus to determine whether the packets collectively form a valid transaction of the identified type.

公开(公告)号：US20180088645A1

公开(公告)日：2018-03-29

申请号：US15807487

申请日：2017-11-08

申请人： UNIVERSITY OF SOUTHERN CALIFORNIA

发明人： Young H. Cho ,  Siddharth S. Bhargav ,  Andrew Goodney

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/26 ,  G06F1/3203 ,  G06F11/3003 ,  G06F11/3027 ,  G06F11/3062 ,  G06F11/3089 ,  G06F11/3466 ,  G06F11/348 ,  G06F17/5022 ,  G06F17/5031 ,  G06F17/5036 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2217/78 ,  G06F2217/84 ,  Y02D10/34

摘要： A digital integrated circuit comprising may include a digital sensor circuit that converts binary bit patterns of wires in a sub-circuit over a given time into a single integer value that represents the total activity of a sub-circuit, and a digital data processing circuit that receives multiple activity integer values from multiple digital sensors in multiple sub-circuits and logically combines the values or uses a lookup table to output a single integer value that represents the total activity of a larger sub-circuit.

公开(公告)号：US09921997B2

公开(公告)日：2018-03-20

申请号：US15089403

申请日：2016-04-01

申请人： Intel Corporation

发明人： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

IPC分类号： G06F13/42 ,  G06F12/02 ,  G06F13/40 ,  G06F3/06 ,  G06F11/30 ,  G06F11/22

CPC分类号： G06F13/4282 ,  G06F3/0664 ,  G06F3/0688 ,  G06F11/221 ,  G06F11/2221 ,  G06F11/3027 ,  G06F12/0246 ,  G06F13/4022 ,  G06F2212/7201

摘要： A mechanism for PCIe cable topology discovery in a Rack Scale Architecture (RSA) and associated methods, apparatus, and systems. Pooled system drawers installed in rack are interconnected via multiple PCIe cables coupled to PCIe ports on the pooled system drawers. The PCIe ports are associated with host ports connections between server nodes and host ports in respective pooled system drawers are automatically detected, with corresponding PCIe connection information being automatically generated and aggregated to determine the PCIe cable topology for the rack. In one aspect, PCIe devices are emulated for each host port in a pooled storage drawer including pooled PCIe storage devices. Server nodes in a pooled compute drawer send PCIe configuration messages over the PCIe cables, with returned reply messages generated by the emulated PCIe devices identifying the host ports. Information pertaining to the host ports, pooled system drawers, and server nodes is used to determine the PCIe cable topology.

公开(公告)号：US09886405B1

公开(公告)日：2018-02-06

申请号：US14672658

申请日：2015-03-30

申请人： Amazon Technologies, Inc.

发明人： Robert Michael Johnson ,  Marc John Brooker ,  Marc Stephen Olson ,  Mark Bradley Davis ,  Nobert Paul Kusters

IPC分类号： G06F3/00 ,  G06F13/38 ,  G06F3/06 ,  G06F13/42 ,  G06F11/14 ,  G06F11/30

CPC分类号： G06F13/387 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/067 ,  G06F11/1443 ,  G06F11/3027 ,  G06F11/3037 ,  G06F13/423 ,  G06F2201/815

摘要： Server computers may include one or more input/output (I/O) adapter devices for communicating with a network and/or direct-attached device. The I/O adapter device may implement processes to manage write requests in a general and flexible manner. The I/O adapter device may also implement processes to manage write requests in a fast an efficient—that is, low latency—manner. Low latency write requests processes may include determining that a write packet for a write request can be processed without additional assistance from a processor, once a processor has initiated a memory access request to fetch write data and also generated protocol information for transmitting the write packet. The I/O adapter device may then process and transmit the write packet through an offload pipeline, without interrupting a processor.