公开(公告)号：US20230110696A1

公开(公告)日：2023-04-13

申请号：US17893333

申请日：2022-08-23

申请人： Fujitsu Limited ,  Inter-University Research Institute Corporation Research Organization of Information and Systems

发明人： Yi Ge ,  Masahiro Goshima

IPC分类号： G06F12/0811 ,  G06F12/0844

摘要： A processor includes request issuing units issuing an access request to a storage, a data array including banks holding sub data divided from data read from the storage based on the access request, a switch to transfer the access request to one of the banks, and first and second determination units. The first determination unit determines a cache hit when a tag address included in the access address matches a tag address held therein in correspondence with an index address included in the access address. The second determination unit determines a cache hit when identification information corresponding to a first tag address included in the access address and a second tag address included in the access address, match identification information and second tag address held therein. A cache controller makes access to the data array or storage, based on a determination result of the first or second determination unit.

公开(公告)号：US20220300289A1

公开(公告)日：2022-09-22

申请号：US17666829

申请日：2022-02-08

申请人： FUJITSU LIMITED ,  Inter-University Research Institute Corporation Research Organization of Information and Systems

发明人： Masahiro Goshima ,  Yi Ge

IPC分类号： G06F9/30 ,  G06F9/38

摘要： An operation processing apparatus including one or more lanes each of which processes at most one element operation of an instruction per cycle, and an element operation issuing unit that issues the element operation to the one or more lanes, wherein an entirety of the operation processing apparatus is separated into a plurality of sections by buffers including a plurality of entries, zero or more of the sections that are unable to continue processing of element operations stop the processing, and remaining sections each continue the processing of element operations by storing element operations proceeding to the downstream section into the immediately downstream buffer.