公开(公告)号：US20060020865A1

公开(公告)日：2006-01-26

申请号：US11188159

申请日：2005-07-22

Applicant: Fa Dai ,  Charles Stroud

Inventor： Fa Dai ,  Charles Stroud

IPC: G06F11/00

CPC classification number: G01R31/31813 ,  G01R31/3167

Abstract: A built-in-self test (BIST) scheme for analog circuitry functionality tests such as frequency response, gain, cut-off frequency, signal-to-noise ratio, and linearity measurement. The BIST scheme utilizes a built-in direct digital synthesizer (DDS) as the test pattern generator that can generate various test waveforms such as chirp, ramp, step frequency, two-tone frequencies, sweep frequencies, MSK, phase modulation, amplitude modulation, QAM and other hybrid modulations. The BIST scheme utilizes a multiplier followed by an accumulator as the output response analyzer (ORA). The multiplier extracts the spectrum information at the desired frequency without using Fast Fourier Transform (FFT) and the accumulator picks up the DC component by averaging the multiplier output.

Abstract translation: 用于模拟电路功能测试的内置自测（BIST）方案，如频率响应，增益，截止频率，信噪比和线性度测量。 BIST方案利用内置的直接数字合成器（DDS）作为测试模式发生器，可以生成各种测试波形，如啁啾，斜坡，步进频率，双音频率，扫频，MSK，相位调制，幅度调制， QAM等混合调制。 BIST方案利用一个乘数跟随一个累加器作为输出响应分析器（ORA）。 乘法器在不使用快速傅里叶变换（FFT）的情况下以期望的频率提取频谱信息，并且累加器通过对乘法器输出求平均值来拾取直流分量。

公开(公告)号：US07428683B2

公开(公告)日：2008-09-23

申请号：US11188159

申请日：2005-07-22

Applicant: Fa Dai ,  Charles E. Stroud

Inventor： Fa Dai ,  Charles E. Stroud

IPC: G01R31/316 ,  G01R31/40

CPC classification number: G01R31/31813 ,  G01R31/3167

Abstract: A built-in-self test (BIST) scheme for analog circuitry functionality tests such as frequency response, gain, cut-off frequency, signal-to-noise ratio, and linearity measurement. The BIST scheme utilizes a built-in direct digital synthesizer (DDS) as the test pattern generator that can generate various test waveforms such as chirp, ramp, step frequency, two-tone frequencies, sweep frequencies, MSK, phase modulation, amplitude modulation, QAM and other hybrid modulations. The BIST scheme utilizes a multiplier followed by an accumulator as the output response analyzer (ORA). The multiplier extracts the spectrum information at the desired frequency without using Fast Fourier Transform (FFT) and the accumulator picks up the DC component by averaging the multiplier output.

Abstract translation: 用于模拟电路功能测试的内置自测（BIST）方案，如频率响应，增益，截止频率，信噪比和线性度测量。 BIST方案利用内置的直接数字合成器（DDS）作为测试模式发生器，可以生成各种测试波形，如啁啾，斜坡，步进频率，双音频率，扫频，MSK，相位调制，幅度调制， QAM等混合调制。 BIST方案利用一个乘数跟随一个累加器作为输出响应分析器（ORA）。 乘法器在不使用快速傅里叶变换（FFT）的情况下以期望的频率提取频谱信息，并且累加器通过对乘法器输出求平均值来拾取直流分量。

公开(公告)号：US20060020649A1

公开(公告)日：2006-01-26

申请号：US11187365

申请日：2005-07-22

Applicant: Fa Dai

Inventor： Fa Dai

IPC: G06F1/02

CPC classification number: H03M7/3042 ,  G06F1/0328 ,  G06F1/0342 ,  H03L7/16 ,  H03M7/3026

Abstract: A direct digital synthesis (DDS) circuit utilizes high order delta-sigma interpolators to remove frequency, phase and amplitude domain quantization errors. The DDS employs an n-bit accumulator operative for receiving an input frequency word (FCW) representing the desired frequency output and converts the frequency word to phase information based upon the clock frequency of the DDS. A high-order delta-sigma interpolator is configured in frequency, phase or amplitude domain to noise-shape the quantization errors through a unit defined by the transfer function of 1-(1−z−1)k in either a feedforward or feedback manner. The delta-sigma interpolator of any order can be implemented using a single-stage pipelined topology with noise transfer function of (1−z−1)k. The DDS circuit also includes digital-to-analog converters (DACs) that convert the outputted sine and cosine amplitude words to analog sinusoidal quardrature signals; and deglitch analog low-pass filters that remove the small glitches due to data conversion.

Abstract translation: 直接数字合成（DDS）电路利用高阶Δ-sigma内插器去除频率，相位和幅度域量化误差。 DDS使用n位累加器，用于接收表示所需频率输出的输入频率字（FCW），并根据DDS的时钟频率将频率字转换为相位信息。 高阶delta-sigma内插器被配置在频率，相位或幅度域中，以通过由1-（1-z）的传递函数定义的单位噪声地形成量化误差， SUP> k 以前馈或反馈方式。 任何次序的Δ-sigma内插器都可以使用具有（1-z≤-SUP）的噪声传递函数的单级流水线拓扑来实现。 DDS电路还包括将输出的正弦和余弦振幅字转换为模拟正弦曲线信号的数模转换器（DAC）; 以及去掉由于数据转换引起的小毛刺的模拟低通滤波器。

公开(公告)号：US07577695B2

公开(公告)日：2009-08-18

申请号：US11187365

申请日：2005-07-22

Applicant: Fa Dai

Inventor： Fa Dai

IPC: G06F1/02

CPC classification number: H03M7/3042 ,  G06F1/0328 ,  G06F1/0342 ,  H03L7/16 ,  H03M7/3026

Abstract: A direct digital synthesis (DDS) circuit utilizes high order delta-sigma interpolators to remove frequency, phase and amplitude domain quantization errors. The DDS employs an n-bit accumulator operative for receiving an input frequency word (FCW) representing the desired frequency output and converts the frequency word to phase information based upon the clock frequency of the DDS. A high-order delta-sigma interpolator is configured in frequency, phase or amplitude domain to noise-shape the quantization errors through a unit defined by the transfer function of 1-(1−z−1)k in either a feedforward or feedback manner. The delta-sigma interpolator of any order can be implemented using a single-stage pipelined topology with noise transfer function of (1−z−1)k. The DDS circuit also includes digital-to-analog converters (DACs) that convert the outputted sine and cosine amplitude words to analog sinusoidal quardrature signals; and deglitch analog low-pass filters that remove the small glitches due to data conversion.

Abstract translation: 直接数字合成（DDS）电路利用高阶Δ-sigma内插器去除频率，相位和幅度域量化误差。 DDS使用n位累加器，用于接收表示所需频率输出的输入频率字（FCW），并根据DDS的时钟频率将频率字转换为相位信息。 将高阶Δ-sigma内插器配置在频率，相位或幅度域中，以通过以前馈或反馈方式由1-（1-z-1）k的传递函数定义的单位来噪声地形成量化误差 。 可以使用具有（1-z-1）k的噪声传递函数的单级流水线拓扑来实现任何顺序的Δ-sigma内插器。 DDS电路还包括将输出的正弦和余弦振幅字转换为模拟正弦曲线信号的数模转换器（DAC）; 以及去掉由于数据转换引起的小毛刺的模拟低通滤波器。

公开(公告)号：US07224911B2

公开(公告)日：2007-05-29

申请号：US10161747

申请日：2002-06-05

Applicant: Fa Dai ,  Mark A. Pacek

Inventor： Fa Dai ,  Mark A. Pacek

IPC: H04B10/00

CPC classification number: H04B10/25133 ,  H04B10/2572 ,  H04B2210/252

Abstract: An apparatus for adaptively receiving, compensating, and transmitting data in optical fiber communication networks are provided. A receiver according to this invention includes at least one optical device for compensating distortion in a channel of an optical signal, at least one photodetector circuit for converting the optical signal into an electrical signal, at least one electronic device for further compensating the distortion in the electronic signal, a clock and data recovery circuit for generating a recovered data signal and a clock signal from the electronic signal, and a post-processing circuit.

Abstract translation: 提供一种用于在光纤通信网络中自适应地接收，补偿和发送数据的装置。 根据本发明的接收机包括用于补偿光信号的通道中的失真的至少一个光学装置，至少一个用于将光信号转换为电信号的光电检测器电路，至少一个电子装置，用于进一步补偿光信号中的失真 电子信号，用于从电子信号产生恢复的数据信号和时钟信号的时钟和数据恢复电路，以及后处理电路。

公开(公告)号：US06975687B2

公开(公告)日：2005-12-13

申请号：US09883539

申请日：2001-06-18

Applicant: Thomas Jackson ,  George Eapen ,  Fa Dai

Inventor： Thomas Jackson ,  George Eapen ,  Fa Dai

IPC: H03F3/24 ,  H04L27/36 ,  H04K1/02 ,  H03C1/52 ,  H04L27/04

CPC classification number: H03F3/24 ,  H03F2200/331 ,  H04L27/2082 ,  H04L27/361

Abstract: A vector modulator including an offset QPSK modulator operative for receiving input data and generating a first output signal representing the modulation to be imposed on a carrier signal to effect offset QPSK modulation of the input signal and a second output signal representing an amplitude of the input data; and a frequency modulator including a sigma-delta modulator, operative for receiving the first output signal generated by the offset QPSK modulator, and generating a control signal representing the desired frequency of the carrier signal such that the carrier signal represents the input signal offset QPSK modulated. The vector modulator also includes a phase-lock loop circuit having a voltage controlled oscillator for generating the carrier signal and a programmable frequency divider for receiving the control signal as an input signal and for changing the frequency of the carrier signal in accordance with the control signal, and an amplifier having a variable gain which is operative for receiving and amplifying the carrier signal output by the phase-lock loop circuit in accordance with the amplitude of the second output signal.

Abstract translation: 一种矢量调制器，包括：偏移QPSK调制器，用于接收输入数据并产生表示要施加在载波信号上的调制的第一输出信号，以实现输入信号的偏移QPSK调制;以及第二输出信号，其表示输入数据的幅度 ; 以及包括Σ-Δ调制器的频率调制器，用于接收由偏移QPSK调制器产生的第一输出信号，并产生表示载波信号的期望频率的控制信号，使得载波信号表示输入信号偏移QPSK调制 。 矢量调制器还包括锁相环电路，其具有用于产生载波信号的压控振荡器和用于接收控制信号作为输入信号的可编程分频器，并根据控制信号改变载波信号的频率 以及具有可变增益的放大器，其可操作用于根据第二输出信号的幅度来接收和放大由锁相环电路输出的载波信号。