中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

205 records (took 0.017 seconds)

    PHASE CONSISTENT NUMERICALLY CONTROLLED OSCILLATOR
    1.
    发明公开
    PHASE CONSISTENT NUMERICALLY CONTROLLED OSCILLATOR 审中-公开

    公开(公告)号：US20240187007A1

    公开(公告)日：2024-06-06

    申请号：US18060856

    申请日：2022-12-01

    Applicant: Analog Devices International Unlimited Company

    Inventor： Krishnan Unni Unnikrishnapillai

    IPC: H03L7/099 ,  G06F1/03

    CPC classification number: H03L7/0994 ,  G06F1/0328 ,  H03L7/0992 ,  H03M1/12

    Abstract: A numerically controlled oscillator system for maintaining a consistent phase reference while switching data rates may include a numerically controlled oscillator (NCO) circuit. The NCO circuit may include a phase accumulator, a phase-to-signal mapping circuit, and a first free-running counter. The phase accumulator may receive a new phase value as an input in response to an update signal. The phase-to-signal mapping circuit may map a value from the phase accumulator to a periodic signal. The first free-running counter may continue counting, without being reset, while the numerically controlled oscillator system is switching digital data rates. The first free-running counter may be configured to provide the new phase value to the phase accumulator using a representation of a counter value of the first free-running counter and a frequency tuning word defined by a representation of a frequency of the periodic signal.

    Coherent signal source
    3.
    发明授权
    Coherent signal source 有权

    公开(公告)号：US09654124B1

    公开(公告)日：2017-05-16

    申请号：US15011306

    申请日：2016-01-29

    Applicant: Keysight Technologies, Inc.

    Inventor： Keith F. Anderson ,  Jean-Pierre Teyssier

    IPC: H03L7/24 ,  H03L7/197

    CPC classification number: H03L7/24 ,  G06F1/022 ,  G06F1/0328 ,  H03L7/1974 ,  H03L7/23

    Abstract: An apparatus, a signal source, and a method for operating the same are disclosed. The apparatus includes a first signal source, a port, controller, signal synthesizer, and a first timestamp register. The port is adapted to receive a first clock signal that includes a sequence of pulses at a constant clock frequency. The signal synthesizer generates an output signal in response to inputs from the controller, the output signal having a first frequency. The first timestamp register counts pulses from the first clock signal. The controller is adapted to receive a command to change the output signal frequency from the first frequency to a second frequency, the controller causing the signal synthesizer to change the output signal frequency to the second frequency and to generate a frequency change timestamp from the timestamp register indicating a time at which the output signal changed from the first frequency to the second frequency.

    DYNAMIC EVALUATION AND ADAPTION OF HARDWARE HASH FUNCTIONS
    5.
    发明申请
    DYNAMIC EVALUATION AND ADAPTION OF HARDWARE HASH FUNCTIONS 有权
    动态评估和硬件哈希函数的自适应

    公开(公告)号：US20160124865A1

    公开(公告)日：2016-05-05

    申请号：US14993583

    申请日：2016-01-12

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Sascha JUNGHANS ,  Matthias KLEIN ,  Thomas SCHLIPF

    IPC: G06F12/10

    CPC classification number: G06F7/544 ,  G06F1/0328 ,  G06F1/1615 ,  G06F7/57 ,  G06F9/3838 ,  G06F12/1018 ,  G06F17/30109 ,  G06F17/30949 ,  G06F2212/401

    Abstract: Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.

    Abstract translation: 基于输入向量的位值创建哈希值。 一种装置包括第一和第二散列表，第一和第二散列函数发生器，其适于基于输入向量的位值来配置用于创建第一和第二散列值的相应散列函数。 哈希值存储在相应的散列表中。 评估单元包括比较单元，用于比较第一散列函数和第二散列函数的相应有效性，以及响应于比较单元的交换单元，适于通过第二散列函数来替换第一散列函数。

    Pipelined phase accumulator
    6.
    发明授权
    Pipelined phase accumulator 有权
    流水线相位累加器

    公开(公告)号：US09244885B1

    公开(公告)日：2016-01-26

    申请号：US13837050

    申请日：2013-03-15

    Applicant: Xilinx, Inc.

    Inventor： Gordon I. Old ,  Andrew Whyte

    IPC: G06F17/10

    CPC classification number: G06F1/0328

    Abstract: An apparatus relating generally to accumulation is disclosed. In this apparatus, a first subtraction-bypass stage is coupled to receive an input operand and a modulus operand to provide a first difference and the input operand. An accumulation stage is coupled to the first subtraction-bypass stage to receive the first difference and the input operand. The accumulation stage is coupled to receive an offset operand for providing an offset-accumulated result. A second subtraction-bypass stage is coupled to receive the offset operand and the modulus operand to provide a second difference and the offset operand. A consolidation stage is coupled to receive the offset operand, the second difference and the offset-accumulated result to provide a consolidated accumulated result. The first subtraction-bypass stage, the accumulation stage, the second subtraction-bypass stage, and the consolidation stage are for a redundant number system.

    Abstract translation: 公开了一般涉及积累的装置。 在该装置中，第一减法旁路级被耦合以接收输入操作数和模数操作数以提供第一差值和输入操作数。 累积级耦合到第一减法旁路级以接收第一差值和输入操作数。 累加阶段被耦合以接收用于提供偏移累积结果的偏移操作数。 耦合第二减法旁路级以接收偏移操作数和模数操作数以提供第二差值和偏移操作数。 耦合整合级以接收偏移操作数，第二差和偏移累加结果以提供合并累积结果。 第一减法旁路级，累积级，第二减法旁路级和合并级用于冗余数字系统。

    Frequency synthesizer and frequency synthesizing method for converting frequency's spurious tones into noise
    7.
    发明授权
    Frequency synthesizer and frequency synthesizing method for converting frequency's spurious tones into noise 有权
    频率合成器和频率合成方法，用于将频率的伪噪声转换为噪声

    公开(公告)号：US09128536B2

    公开(公告)日：2015-09-08

    申请号：US13412653

    申请日：2012-03-06

    Applicant: Liming Xiu ,  Ming-Chieh Lin

    Inventor： Liming Xiu ,  Ming-Chieh Lin

    IPC: G06F1/02 ,  G06F1/03 ,  G06F1/025

    CPC classification number: G06F1/025 ,  G06F1/02 ,  G06F1/022 ,  G06F1/0328

    Abstract: One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise.

    Abstract translation: 直接频率合成技术（例如飞行加法器结构）的优点之一是其通过利用时间平均频率概念产生任意频率的能力。 在直接频率合成器的时钟输出中，代替一种类型的周期，有两种类型的周期。 与其中时钟能量集中在其设计频率的常规单周期时钟不同，基于时间 - 平均频率的时钟将其一些能量扩展到伪噪声，这可能对某些应用有害。 伪噪声是由频率合成器内的分数分量累加器产生的周期性进位序列引起的。 本发明提出了一种破坏这种周期性并将伪噪声转换成宽带噪声的方法和装置。

    Method and apparatus for reducing signal edge jitter in an output signal from a numerically controlled oscillator
    10.
    发明授权
    Method and apparatus for reducing signal edge jitter in an output signal from a numerically controlled oscillator 有权
    用于减少来自数控振荡器的输出信号中的信号边缘抖动的方法和装置

    公开(公告)号：US08775491B2

    公开(公告)日：2014-07-08

    申请号：US13367834

    申请日：2012-02-07

    Applicant: Alexander Buhmann ,  Marian Keck

    Inventor： Alexander Buhmann ,  Marian Keck

    IPC: G06F1/02 ,  G06F1/03

    CPC classification number: G06F1/0342 ,  G01C19/5776 ,  G06F1/022 ,  G06F1/0328 ,  H03L7/0991

    Abstract: A method for reducing signal edge jitter in an output signal from a numerically controlled oscillator includes processing an input signal with a first accumulator to provide a first accumulator output signal and continuing to use a carry in the processing of the input signal with the first accumulator in the event of an overflow. The method further includes processing the input signal with a second accumulator to provide a second accumulator output signal and rejecting a carry in the processing of the input signal with the second accumulator in the event of an overflow. The method further includes outputting the second accumulator output signal at an output of the numerically controlled oscillator and synchronizing the second accumulator using the first accumulator output signal.

    Abstract translation: 一种用于减少来自数控振荡器的输出信号中的信号边缘抖动的方法包括：利用第一累加器处理输入信号，以提供第一累加器输出信号，并且继续使用与第一累加器对输入信号进行处理的进位 发生溢出事件。 该方法还包括利用第二累加器来处理输入信号以在溢出的情况下提供第二累加器输出信号并且拒绝与第二累加器的输入信号的处理中的进位。 该方法还包括在数控振荡器的输出处输出第二累加器输出信号，并使用第一累加器输出信号使第二累加器同步。

Patent Agency Ranking