公开(公告)号：US09275726B2

公开(公告)日：2016-03-01

申请号：US14200040

申请日：2014-03-07

Applicant: Faraday Technology Corp.

Inventor： Ching-Te Chuang ,  Chih-Hao Chang ,  Chao-Kuei Chung ,  Chien-Yu Lu ,  Shyh-Jye Jou ,  Ming-Hsien Tu

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/413

Abstract: A static memory cell is provided. The static memory cell includes a data latch circuit and a voltage provider. The data latch circuit is configured to store a bit data. The data latch circuit has a first inverter and a second inverter, and the first inverter and the second inverter are coupled to each other. The first inverter and the second inverter respectively receive a first voltage and a second voltage as power voltages. The voltage provider provides the first voltage and the second voltage to the data latch circuit. When the bit data is written to the data latch circuit, the voltage provider adjusts a voltage value of one of the first and second voltages according to the bit data.

Abstract translation: 提供静态存储单元。 静态存储单元包括一个数据锁存电路和一个电压提供器。 数据锁存电路被配置为存储位数据。 数据锁存电路具有第一反相器和第二反相器，并且第一反相器和第二反相器彼此耦合。 第一反相器和第二反相器分别接收第一电压和第二电压作为电源电压。 电压提供器向数据锁存电路提供第一电压和第二电压。 当位数据被写入数据锁存电路时，电压提供器根据位数据调节第一和第二电压之一的电压值。