公开(公告)号：US20170221535A1

公开(公告)日：2017-08-03

申请号：US15158589

申请日：2016-05-19

Applicant: Faraday Technology Corp.

Inventor： Kun-Chih Chen ,  Hsiao-An Chuang

IPC: G11C7/22 ,  G11C8/06

CPC classification number: G11C8/06 ,  G11C7/1039 ,  G11C7/106 ,  G11C15/00 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2281

Abstract: A non-volatile memory accelerator and a method for speeding up data access are provided. The non-volatile memory accelerator includes a data pre-fetching unit, a cache unit, and an access interface circuit. The data pre-fetching unit has a plurality of line buffers. One of the line buffers provides read data according to a read command, or the data pre-fetching unit reads at least one cache data as the read data according to the read command. The data pre-fetching unit further stores in at least one of the line buffers a plurality of pre-stored data with continuous addresses according to the read command. The cache unit stores the at least one cache data and the pre-stored data with the continuous addresses. The access interface circuit is configured to be an interface circuit of the non-volatile memory.

公开(公告)号：US09773534B2

公开(公告)日：2017-09-26

申请号：US15158589

申请日：2016-05-19

Applicant: Faraday Technology Corp.

Inventor： Kun-Chih Chen ,  Hsiao-An Chuang

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/06

CPC classification number: G11C8/06 ,  G11C7/1039 ,  G11C7/106 ,  G11C15/00 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2281

Abstract: A non-volatile memory accelerator and a method for speeding up data access are provided. The non-volatile memory accelerator includes a data pre-fetching unit, a cache unit, and an access interface circuit. The data pre-fetching unit has a plurality of line buffers. One of the line buffers provides read data according to a read command, or the data pre-fetching unit reads at least one cache data as the read data according to the read command. The data pre-fetching unit further stores in at least one of the line buffers a plurality of pre-stored data with continuous addresses according to the read command. The cache unit stores the at least one cache data and the pre-stored data with the continuous addresses. The access interface circuit is configured to be an interface circuit of the non-volatile memory.