公开(公告)号：US09641159B1

公开(公告)日：2017-05-02

申请号：US15046451

申请日：2016-02-18

Applicant: Faraday Technology Corp.

Inventor： Chiang-Hsiang Liao ,  Sheng-Hua Chen

IPC: H03K3/289 ,  H03K3/037

CPC classification number: H03K3/0375 ,  H03K3/0372 ,  H03K3/3562

Abstract: A flip-flop circuit including a first logic circuit, a first master latch, a second master latch, and a slave latch is provided. The first logic circuit operates a logic operation on a selecting signal and a clock signal to generate a first control signal. The first master latch receives a data signal according to the first control signal and latches the data signal according to the selecting signal and the clock signal. The second master latch receives a scan data signal according to the selecting signal and the clock signal, wherein an output terminal of the second master latch is directly connected to an output terminal of the first master latch. The slave latch latches a signal on the output terminals of the first and second master latches for generating an output signal.

公开(公告)号：US20170126212A1

公开(公告)日：2017-05-04

申请号：US15046451

申请日：2016-02-18

Applicant: Faraday Technology Corp.

Inventor： Chiang-Hsiang Liao ,  Sheng-Hua Chen

IPC: H03K3/037

CPC classification number: H03K3/0375 ,  H03K3/0372 ,  H03K3/3562

Abstract: A flip-flop circuit including a first logic circuit, a first master latch, a second master latch, and a slave latch is provided. The first logic circuit operates a logic operation on a selecting signal and a clock signal to generate a first control signal. The first master latch receives a data signal according to the first control signal and latches the data signal according to the selecting signal and the clock signal. The second master latch receives a scan data signal according to the selecting signal and the clock signal, wherein an output terminal of the second master latch is directly connected to an output terminal of the first master latch. The slave latch latches a signal on the output terminals of the first and second master latches for generating an output signal.