公开(公告)号：US09484085B1

公开(公告)日：2016-11-01

申请号：US15098329

申请日：2016-04-14

Applicant: Faraday Technology Corporation ,  Faraday Technology Corp.

Inventor： Zhao-Yong Zhang ,  Kun-Ti Lee

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A static memory apparatus and a static memory cell thereof are provided. The static memory cell includes a data latch circuit, a data write-in circuit and a data read-out circuit. The data latch circuit has a first tristate output inverting circuit and a second tristate output inverting circuit. The data write-in circuit provides a first reference voltage to a power receiving terminal of a selected tristate output inverting circuit which is one of the first and second tristate output inverting circuits, and provides a second reference voltage to an input terminal of the selected tristate output inverting circuit during a data write-in time period. The data read-out circuit generates read-out data according to a voltage at an output terminal of the second tristate output inverting circuit and the second reference voltage during a data read-out time period.

Abstract translation: 提供了一种静态存储装置及其静态存储单元。 静态存储单元包括数据锁存电路，数据写入电路和数据读出电路。 数据锁存电路具有第一三态输出反相电路和第二三态输出反相电路。 数据写入电路向作为第一和第二三态输出反相电路之一的所选三态输出反相电路的功率接收端提供第一参考电压，并向所选三态输入端的输入端提供第二参考电压 在数据写入期间输出反相电路。 数据读出电路根据数据读出期间的第二三态输出反相电路的输出端的电压和第二基准电压来生成读出数据。

公开(公告)号：US09240228B1

公开(公告)日：2016-01-19

申请号：US14457125

申请日：2014-08-12

Applicant: Faraday Technology Corp.

Inventor： Biao Chen ,  Zhao-Yong Zhang ,  Hao Wu ,  Kun-Ti Lee

IPC: G11C7/04 ,  G11C7/12 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/06 ,  G11C7/14 ,  G11C11/419

Abstract: A static memory apparatus and a data reading method thereof are provided. The static memory apparatus includes a plurality of memory cells, a plurality of dummy memory cells, a sense amplifier, and a discharge current adjuster. The dummy memory cells respectively include a plurality discharge ends for discharging charges on a dummy bit line. The sense amplifier is enabled for a sensing and amplifying operation according to a signal on the dummy bit line, and the sense amplifier generates readout data accordingly. The discharge current adjuster adjusts at least one discharge current on at least one controlled discharge end according to an operating voltage of the memory cells.

Abstract translation: 提供了一种静态存储装置及其数据读取方法。 静态存储装置包括多个存储单元，多个虚拟存储单元，读出放大器和放电电流调节器。 虚拟存储单元分别包括用于在虚拟位线上放电的多个放电端。 读出放大器根据虚拟位线上的信号被使能用于感测和放大操作，并且读出放大器相应地产生读出数据。 放电电流调节器根据存储单元的工作电压在至少一个受控放电端调节至少一个放电电流。