公开(公告)号：US06643821B2

公开(公告)日：2003-11-04

申请号：US09726927

申请日：2000-11-30

申请人： Faraydon O. Karim ,  Kartik V. Talsania ,  Vincent E. Wass

发明人： Faraydon O. Karim ,  Kartik V. Talsania ,  Vincent E. Wass

IPC分类号： G06F1100

CPC分类号： H03M13/096

摘要： A method and a computing system compute an incremental checksum corresponding to a data packet. The incremental checksum is computed within one processor cycle of a processor. A first register (102) stores first checksum information corresponding to a data packet. A second register (104) stores second checksum information corresponding to old information being deleted from the data packet. A third register (106) stores third checksum information corresponding to new information being added to the data packet. An incremental checksum circuit (100), electrically connected to the first register (102), to the second register (104), and to the third register (106), provides resulting checksum information corresponding to the data packet after deleting the old information from the data packet and adding the new information to the data packet. The resulting checksum information is selectively stored in the first register (102).