公开(公告)号：US20110298416A1

公开(公告)日：2011-12-08

申请号：US12960365

申请日：2010-12-03

申请人： Fateh SINGH ,  Emeric UGUEN

发明人： Fateh SINGH ,  Emeric UGUEN

IPC分类号： H02J7/00 ,  H03L7/00 ,  H02M3/22 ,  G06F1/04

CPC分类号： H03L7/197

摘要： A clock signal generator comprising an input pin for receiving an oscillating signal and an output pin for providing a clock signal. The clock signal generator also comprises a frequency divider connected between the input pin and the output pin. The frequency divider having a plurality of frequency division factors associated therewith, wherein, in use, the frequency divider is configured to apply one of the plurality of frequency division factors as an in-use frequency division factor to the oscillating signal in order to generate the clock signal. The clock signal generator further comprising a controller configured to periodically replace the in-use frequency division factor with another of the plurality of frequency division factors.

摘要翻译： 一种时钟信号发生器，包括用于接收振荡信号的输入引脚和用于提供时钟信号的输出引脚。 时钟信号发生器还包括连接在输入引脚和输出引脚之间的分频器。 所述分频器具有与其相关联的多个分频因子，其中在使用中，分频器被配置为将多个分频因子中的一个作为使用中的分频因子施加到振荡信号，以便产生 时钟信号。 所述时钟信号发生器还包括控制器，所述控制器被配置成周期性地用所述多个频率分频因子中的另一个替换所述使用中的分频因子。