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1.发明授权Method of making a via filled dual damascene structure without middle stop layer 有权制造通孔填充双镶嵌结构而不具有中间停止层的方法公开(公告)号：US06372631B1
公开(公告)日：2002-04-16
申请号：US09778061
申请日：2001-02-07
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031
摘要： An interconnect structure and method of forming the same in which a barrier diffusion layer/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the barrier diffusion layer/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a via in the first dielectric layer. An organic low k dielectric material is deposited within the via and over the first dielectric layer to form a second dielectric layer over the via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. A portion of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译： 一种互连结构及其形成方法，其中阻挡扩散层/蚀刻停止层沉积在导电层上。 将无机低k电介质材料沉积在阻挡扩散层/蚀刻停止层上以形成第一介电层。 蚀刻第一介电层以在第一介电层中形成通孔。 有机低k介电材料沉积在通孔内和第一介电层上方，以在通孔和第一介电层上形成第二电介质层。 再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽的一部分直接在通孔的上方。 重新打开的通孔和沟槽填充有导电材料。
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2.发明授权Method of making a slot via filled dual damascene structure with a middle stop layer 有权通过具有中间停止层的填充双镶嵌结构制造槽的方法公开(公告)号：US06444573B1
公开(公告)日：2002-09-03
申请号：US09788472
申请日：2001-02-21
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , Y10S977/888
摘要： An interconnect structure and method of forming the same in which a first inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. A second low k dielectric material is deposited within the slot via and over the etch stop layer, to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is over the via that is etched. The re-opened via and the trench are filled with a conductive material.
摘要翻译： 一种互连结构及其形成方法，其中第一无机低k电介质材料沉积在导电层上以形成第一介电层。 在第一电介质层上形成蚀刻停止层。 蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成槽通孔。 狭缝通孔比随后形成的沟槽的宽度长。 第二低k电介质材料通过蚀刻停止层上方和上方沉积在槽内，以在槽通孔和蚀刻停止层上形成第二电介质层。 再填充的槽通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽的整个宽度在被蚀刻的通孔之上。 重新打开的通孔和沟槽填充有导电材料。
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3.发明授权Method of making a slot via filled dual damascene structure with middle stop layer 有权通过具有中间停止层的填充双镶嵌结构制作槽的方法公开(公告)号：US06365505B1
公开(公告)日：2002-04-02
申请号：US09780531
申请日：2001-02-21
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808
摘要： A method of forming an interconnect structure in which an inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. An organic low k dielectric material is deposited within the slot via and over the etch stop layer to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译： 一种形成互连结构的方法，其中无机低k电介质材料沉积在导电层上以形成第一介电层。 在第一电介质层上形成蚀刻停止层。 蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成槽通孔。 狭缝通孔比随后形成的沟槽的宽度长。 有机低k电介质材料通过蚀刻停止层上方和上方沉积在槽内，以在缝隙通孔和蚀刻停止层上形成第二电介质层。 再填充的槽通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽的整个宽度直接在通孔上方。 重新打开的通孔和沟槽填充有导电材料。
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4.发明授权Method of making a slot via filled dual damascene structure with middle stop layer 有权通过具有中间停止层的填充双镶嵌结构制作槽的方法公开(公告)号：US06391766B1
公开(公告)日：2002-05-21
申请号：US09788641
申请日：2001-02-21
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031
摘要： A method of forming an interconnect structure in which an organic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. An inorganic low k dielectric material is deposited within the slot via and over the etch stop layer to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译： 一种形成互连结构的方法，其中有机低k介电材料沉积在导电层上以形成第一介电层。 在第一电介质层上形成蚀刻停止层。 蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成槽通孔。 狭缝通孔比随后形成的沟槽的宽度长。 无机低k介电材料通过蚀刻停止层上方和上方沉积在槽内，以在槽通孔和蚀刻停止层上形成第二电介质层。 再填充的槽通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽的整个宽度直接在通孔上方。 重新打开的通孔和沟槽填充有导电材料。
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5.发明授权Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning 有权使用CVD有机BARC形成互连结构以减轻中毒的方法公开(公告)号：US06632707B1
公开(公告)日：2003-10-14
申请号：US10058227
申请日：2002-01-29
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
IPC分类号： H01L2144
CPC分类号： H01L21/76808
摘要： A method for forming a metal interconnect structure in a semiconductor device with the elimination of via poisoning during trench mask formation employs a CVD organic BARC that isolates the low k dielectric film. The CVD organic BARC is deposited over the low k dielectric film and in the via hole. Once the trench mask has been formed on the CVD organic BARC, the CVD organic BARC may be removed in the same process as the photoresist of the trench mask layer. A properly formed trench will have been created since the via poisoning and resist scumming were substantially eliminated by the presence of the CVD organic BARC.
摘要翻译： 在沟槽掩模形成期间消除通孔中毒的在半导体器件中形成金属互连结构的方法使用隔离低k绝缘膜的CVD有机BARC。 CVD有机BARC沉积在低k电介质膜和通孔中。 一旦在CVD有机BARC上形成了沟槽掩模，就可以以与沟槽掩模层的光致抗蚀剂相同的工艺去除CVD有机BARC。 由于CVD有机BARC的存在基本上消除了通孔中毒和抵抗浮渣，所以将形成一个正确形成的沟槽。
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6.发明授权Slot via filled dual damascene interconnect structure without middle etch stop layer 有权通过填充的双镶嵌互连结构的槽，没有中间蚀刻停止层公开(公告)号：US06603206B2
公开(公告)日：2003-08-05
申请号：US10105509
申请日：2002-03-26
IPC分类号： H01L23522
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031 , Y10S977/827
摘要： An interconnect structure and method of forming the same in which a bottom anti-reflective coating/etch stop layer is deposited over a conductive layer. An inorganic low k dielectric material is deposited over the BARC/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a slot via in the first dielectric layer. An organic low k dielectric material is deposited within the slot via and over the first dielectric layer to form a second dielectric layer over the slot via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. The trench extends in a direction that is normal to the length of the slot via. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译： 一种互连结构及其形成方法，其中底部抗反射涂层/蚀刻停止层沉积在导电层上。 无机低k介电材料沉积在BARC /蚀刻停止层上以形成第一介电层。 蚀刻第一介电层以在第一介电层中形成槽通孔。 有机低k电介质材料通过第一电介质层和第一介电层上方沉积在槽内，以在槽通孔和第一介电层上形成第二电介质层。 再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽沿与槽通孔的长度垂直的方向延伸。 沟槽的整个宽度直接在通孔上方。 重新打开的通孔和沟槽填充有导电材料。
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7.发明授权Via filled dual damascene structure with middle stop layer and method for making the same 有权通过填充中间停止层的双镶嵌结构和制作相同的方法公开(公告)号：US06521524B1
公开(公告)日：2003-02-18
申请号：US09778070
申请日：2001-02-07
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031
摘要： An interconnect structure and method of forming the same in which an inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a via in the first dielectric layer. An organic low k dielectric material is deposited within the via and over the etch stop layer to form a second dielectric layer over the via and the etch stop layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. A portion of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译： 一种互连结构及其形成方法，其中无机低k电介质材料沉积在导电层上以形成第一介电层。 在第一电介质层上形成蚀刻停止层。 蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成通孔。 有机低k介电材料沉积在通孔内和蚀刻停止层上方，以在通孔和蚀刻停止层上方形成第二电介质层。 再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽的一部分直接在通孔的上方。 重新打开的通孔和沟槽填充有导电材料。
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公开(公告)号：US06465889B1
公开(公告)日：2002-10-15
申请号：US09778109
申请日：2001-02-07
IPC分类号： H01L2348
CPC分类号： H01L21/76808 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The dimensional accuracy of trenches and, hence, the width of metal lines, in damascene interconnection structures is improved by employing silicon carbide as a capping layer/BARC on an underlying metal feature, e.g., Cu. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide capping layer/BARC having an extinction coefficient (k) of about −0.2 to about −0.5, without the need for a middle etch stop layer, thereby improving efficiency by reducing the number of processing steps.
摘要翻译： 通过在下面的金属特征例如Cu上使用碳化硅作为覆盖层/ BARC来改善镶嵌互连结构中的沟槽的尺寸精度以及因此的金属线的宽度。 实施例包括采用采用碳消耗系数（k）约-0.2至约-0.5的碳化硅覆盖层/ BARC的第一沟槽最后双镶嵌技术，而不需要中间蚀刻停止层，从而通过减少 处理步骤数
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9.发明授权Via filled dual damascene structure with middle stop layer and method for making the same 有权通过填充中间停止层的双镶嵌结构和制作相同的方法公开(公告)号：US06465340B1
公开(公告)日：2002-10-15
申请号：US09776734
申请日：2001-02-06
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031
摘要： An interconnect structure and method of forming the same in which a first inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a via in the first dielectric layer. A second low k dielectric material is deposited within the via and over the etch stop layer to form a second dielectric layer over the via and the etch stop layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. A portion of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译： 一种互连结构及其形成方法，其中第一无机低k电介质材料沉积在导电层上以形成第一介电层。 在第一电介质层上形成蚀刻停止层。 蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成通孔。 第二低k电介质材料沉积在通孔内和蚀刻停止层上方，以在通孔和蚀刻停止层之上形成第二电介质层。 再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽的一部分直接在通孔的上方。 重新打开的通孔和沟槽填充有导电材料。
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10.发明授权公开(公告)号：US06429116B1
公开(公告)日：2002-08-06
申请号：US09778064
申请日：2001-02-07
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , H01L23/5226 , H01L23/5329 , H01L23/53295 , H01L2221/1031 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An interconnect structure and method of forming the same in which a diffusion barrier/etch stop layer is deposited over a conductive layer. An organic low k dielectric material is deposited over the diffusin barrier/etch stop layer to form a first dielectric layer. The first dielectric layer is etched to form a slot via in the first dielectric layer. An inorganic low k dielectric material is deposited within the slot via and over the first dielectric layer to form a second dielectric layer over the slot via and the first dielectric layer. The re-filled via is simultaneously etched with the second dielectric layer in which a trench is formed. The trench extends in a direction that is normal to the length of the slot via. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译： 一种互连结构及其形成方法，其中扩散阻挡/蚀刻停止层沉积在导电层上。 将有机低k电介质材料沉积在漫射阻挡层/蚀刻停止层上以形成第一介电层。 蚀刻第一介电层以在第一介电层中形成槽通孔。 无机低k电介质材料通过第一介电层上方和上方沉积在槽内，以在槽通孔和第一介电层上形成第二电介质层。 再次填充的通孔与其中形成沟槽的第二电介质层同时蚀刻。 沟槽沿与槽通孔的长度垂直的方向延伸。 沟槽的整个宽度直接在通孔上方。 重新打开的通孔和沟槽填充有导电材料。
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