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1.发明授权公开(公告)号：US10775433B1
公开(公告)日：2020-09-15
申请号：US16369809
申请日：2019-03-29
发明人： Valentin Ossman , Anthony Kozaczuk , Cheng C. Wang
IPC分类号： G11C11/419 , G01R31/3177 , G06F30/331 , H03K19/17728
摘要： An integrated circuit comprising a field programmable gate array (FPGA) including a plurality of logic tiles wherein each logic tile includes circuitry including (i) logic circuitry and (ii) an interconnect network including a plurality of multiplexers. The FPGA further includes a robust memory cell including: three or more storage elements that are more than one time programmable to store a data state, majority detection circuitry to detect a majority data state stored in the three or more storage elements; and an output, coupled to the majority detection circuitry, to output mode select data which is representative of the majority data state stored in the storage elements. The FPGA also includes mode/function select circuitry to configure a mode of operation of at least a portion of the circuitry in one or more of the plurality of logic tiles based on the mode select data.
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公开(公告)号：US10411712B2
公开(公告)日：2019-09-10
申请号：US16042170
申请日：2018-07-23
发明人： Cheng C. Wang , Anthony Kozaczuk , Valentin Ossman
IPC分类号： H03K19/177 , G06F17/50
摘要： An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation of the field programmable gate array, each logic tile is configurable to connect with at least one logic tile of the plurality of logic tiles, and wherein each logic tile of the plurality of logic tiles includes an interconnect network, including a plurality of multiplexers, and logic circuitry. The field programmable gate array, in a first operational mode, includes a first group of logic tiles that are programmed in a powered-up state wherein each logic tile of the first group of logic tiles consumes electrical power during operation, and a second group of logic tiles of the plurality of logic tiles are programmed in a powered-down state wherein each logic tile of the second group of logic tiles does not consume electrical power during operation.
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公开(公告)号：US10411711B2
公开(公告)日：2019-09-10
申请号：US15975037
申请日：2018-05-09
IPC分类号： H03K19/177 , G06F17/50
摘要： An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O of each logic tile is identical. The physical array includes a first virtual array of logic tiles, programmed to perform data processing operations, including a first plurality of logic tiles of the physical array. The physical array also includes a second virtual array of logic tiles, programmed to perform second operations, including a second plurality of logic tiles of the physical array. The logic tiles of the second plurality are different from the logic tiles of the first plurality. In one embodiment, performance of the data processing operations of the first virtual array is independent from performance of the second operations of the second virtual array.
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公开(公告)号：US10686447B1
公开(公告)日：2020-06-16
申请号：US16374735
申请日：2019-04-03
IPC分类号： H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： An integrated circuit comprising an FPGA including programmable/configurable logic circuitry having a periphery, wherein resources (e.g., memory (e.g., high-speed local RAM), one or more busses, and/or circuitry external to the FPGA (e.g., a processor, a controller and/or system/external memory), is/are disposed outside the periphery of the programmable/configurable logic circuitry which includes a plurality of logic tiles, wherein at least one logic tile is located completely within the interior of the periphery and wherein each logic tile of the array of logic tiles includes a plurality of I/Os located on the perimeter of the logic tile wherein a first portion of the I/Os are located on a perimeter of the logic tile that is interior to the periphery, and the first portion of I/Os of each logic tile of the plurality of the logic tiles are directly connected to the bus to provide communication between the resources and the logic tiles.
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5.发明申请公开(公告)号：US20190028104A1
公开(公告)日：2019-01-24
申请号：US16042170
申请日：2018-07-23
发明人： Cheng C. Wang , Anthony Kozaczuk , Valentin Ossman
IPC分类号： H03K19/177 , G06F17/50
摘要： An integrated circuit comprising a field programmable gate array including a plurality of logic tiles, wherein, during operation of the field programmable gate array, each logic tile is configurable to connect with at least one logic tile of the plurality of logic tiles, and wherein each logic tile of the plurality of logic tiles includes an interconnect network, including a plurality of multiplexers, and logic circuitry. The field programmable gate array, in a first operational mode, includes a first group of logic tiles that are programmed in a powered-up state wherein each logic tile of the first group of logic tiles consumes electrical power during operation, and a second group of logic tiles of the plurality of logic tiles are programmed in a powered-down state wherein each logic tile of the second group of logic tiles does not consume electrical power during operation.
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6.发明申请公开(公告)号：US20180343010A1
公开(公告)日：2018-11-29
申请号：US15975037
申请日：2018-05-09
IPC分类号： H03K19/177 , G06F17/50
CPC分类号： H03K19/1776 , G06F17/5054 , G06F17/5068 , H03K19/17704 , H03K19/17728 , H03K19/17736
摘要： An integrated circuit comprising a physical array of logic tiles, wherein each logic tile includes a perimeter and a plurality of external I/O disposed in a layout on the perimeter of the logic tile wherein the layout of the external I/O of each logic tile is identical. The physical array includes a first virtual array of logic tiles, programmed to perform data processing operations, including a first plurality of logic tiles of the physical array. The physical array also includes a second virtual array of logic tiles, programmed to perform second operations, including a second plurality of logic tiles of the physical array. The logic tiles of the second plurality are different from the logic tiles of the first plurality. In one embodiment, performance of the data processing operations of the first virtual array is independent from performance of the second operations of the second virtual array.
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