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公开(公告)号:US11791771B2
公开(公告)日:2023-10-17
申请号:US17899986
申请日:2022-08-31
发明人: Bei Xiao , Xiao-Lin Huang , Zhi-Qiang Luo
摘要: A method for calibrating a first clock signal output by an oscillation module to obtain a calibrated second clock signal includes obtaining a first count value by counting a third clock signal of an external device. A second count value is obtained by counting a scan signal of the oscillation module, and a first cycle ratio is obtained based on the first count value and the second count value. It is determined whether the first clock signal has a frequency deviation by comparing the first cycle ratio with a reference cycle ratio. A frequency division coefficient of the oscillation module is adjusted when the first clock signal has the frequency deviation, so that the oscillation module divides a frequency of the first clock signal according to the adjusted frequency division coefficient, thereby obtaining the calibrated second clock signal.