公开(公告)号：US20210004265A1

公开(公告)日：2021-01-07

申请号：US17026038

申请日：2020-09-18

申请人： Francesc Guim Bernat ,  Uzair Qureshi ,  Lokpraveen Mosur ,  Kshitij Arun Doshi ,  Ned M. Smith

发明人： Francesc Guim Bernat ,  Uzair Qureshi ,  Lokpraveen Mosur ,  Kshitij Arun Doshi ,  Ned M. Smith

IPC分类号： G06F9/48 ,  G06N20/00 ,  G06N3/08 ,  H02J3/38

摘要： Various aspects of methods, systems,and use cases include coordinating actions at an edge device based on power production in a distributed edge computing environment. Systems and methods may be used to an edge device based on power production. A method may include predicting power harvesting of an edge device over a period of time. The method may determine an optimized timeframe among various timeframes for performing a task based on the predicted power harvesting. The method may include outputting or an indication for use by an implementing edge device.

公开(公告)号：US20210014203A1

公开(公告)日：2021-01-14

申请号：US17032391

申请日：2020-09-25

申请人： Kshitij Arun Doshi ,  Uzair Qureshi ,  Lokpraveen Mosur ,  Patrick Fleming ,  Stephen Doyle ,  Brian Andrew Keating ,  Ned M. Smith

发明人： Kshitij Arun Doshi ,  Uzair Qureshi ,  Lokpraveen Mosur ,  Patrick Fleming ,  Stephen Doyle ,  Brian Andrew Keating ,  Ned M. Smith

IPC分类号： H04L29/06 ,  G06F21/60 ,  G06F13/28

摘要： Methods, systems, and use cases for one-touch inline cryptographic data security are discussed, including an edge computing device with a network communications circuitry (NCC), an enhanced DMA engine coupled to a memory device and including a cryptographic engine, and processing circuitry configured to perform a secure exchange with a second edge computing device to negotiate a shared symmetric encryption key, based on a request for data. An inline encryption command for communication to the enhanced DMA engine is generated. The inline encryption command includes a first address associated with a storage location storing the data, a second address associated with a memory location in the memory device, and the shared symmetric encryption key. The data is retrieved from the storage location using the first address, the data is encrypted using the shared symmetric encryption key, and the encrypted data is stored in the memory location using the second address.

公开(公告)号：US20190044724A1

公开(公告)日：2019-02-07

申请号：US15941407

申请日：2018-03-30

申请人： Kapil Sood ,  Naveen Lakkakula ,  Hari K. Tadepalli ,  Lokpraveen Mosur ,  Rajesh Gadiyar ,  Patrick Fleming

发明人： Kapil Sood ,  Naveen Lakkakula ,  Hari K. Tadepalli ,  Lokpraveen Mosur ,  Rajesh Gadiyar ,  Patrick Fleming

IPC分类号： H04L9/32 ,  H04L9/08 ,  H04L9/14 ,  H04L29/06

摘要： A security accelerator device stores a first credential that is uniquely associated with the individual security accelerator device and represents a root of trust to a trusted entity. The device establishes a cryptographic trust relationship with a client entity that is based on the root of trust, the cryptographic trust relationship being represented by a second credential. The device receives and store a secret credential of the client entity, which is received via communication secured by the second credential. Further, the device executes a cryptographic computation using the secret client credential on behalf of the client entity to produce a computation result.

公开(公告)号：US20210334101A1

公开(公告)日：2021-10-28

申请号：US16933369

申请日：2020-07-20

申请人： Stephen T. Palermo ,  Srihari Makineni ,  Shubha Bommalingaiahnapallya ,  Neelam Chandwani ,  Rany T. Elsayed ,  Udayan Mukherjee ,  Lokpraveen Mosur ,  Adwait Purandare

发明人： Stephen T. Palermo ,  Srihari Makineni ,  Shubha Bommalingaiahnapallya ,  Neelam Chandwani ,  Rany T. Elsayed ,  Udayan Mukherjee ,  Lokpraveen Mosur ,  Adwait Purandare

IPC分类号： G06F9/30 ,  G06F9/38

摘要： Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.

公开(公告)号：US20060075194A1

公开(公告)日：2006-04-06

申请号：US11280585

申请日：2005-11-15

申请人： Lokpraveen Mosur ,  Harikrishna Baliga

发明人： Lokpraveen Mosur ,  Harikrishna Baliga

IPC分类号： G06F12/00

CPC分类号： G06F12/0804

摘要： An apparatus and a method for rapidly flushing a cache memory device, including a list structure to track changes in a cache, which may be implemented on the processor die separate from the cache memory. The list structure allows for access to a relatively small store of data to determine whether or not a cache entry needs to be written to the main memory. Choosing the format of the list structure, allows one to make tradeoffs between area needed on a chip and the amount of efficiency in the cache flushing process.