公开(公告)号：US06748408B1

公开(公告)日：2004-06-08

申请号：US09693057

申请日：2000-10-20

申请人： Francis Bredin ,  Bertrand Gabillard ,  Francois Auguste Roger Meunier

发明人： Francis Bredin ,  Bertrand Gabillard ,  Francois Auguste Roger Meunier

IPC分类号： G06F102

CPC分类号： H03L7/0996 ,  G06F7/68 ,  H03L7/1974

摘要： A non-integer fractional divider divides a reference clock signal having period P by a non-integer ratio K. The divider includes multiplexers to receive a plurality N of clock signals wherein each clock signal is equally phase shifted by a P/N delay. Incrementers coupled to the multiplexers select first and second clock signals between the N clock signals. Such that the phase shift delay between the two selected clock signals is representative of the non-integer value of K. The selected clock signals are combined to output a divided clock signal. The enabling time of each selected clock signal is respectively representative of the duration of the low level and the high level of the divided clock signal.

摘要翻译： 非整数分数分频器将具有周期P的参考时钟信号除以非整数比K.分频器包括多路复用器，用于接收多个N个时钟信号，其中每个时钟信号被相位移P / N延迟。 耦合到多路复用器的增量器在N个时钟信号之间选择第一和第二时钟信号。 使得两个所选择的时钟信号之间的相移延迟代表K的非整数值。所选择的时钟信号被组合以输出分频时钟信号。 每个选择的时钟信号的使能时间分别代表低电平的持续时间和分频时钟信号的高电平。