Multiprocessor computer apparatus employing distributed communications
paths and a passive task register
    1.
    发明授权
    Multiprocessor computer apparatus employing distributed communications paths and a passive task register 失效
    采用分布式通信路径的多处理器计算机装置和被动任务寄存器

    公开(公告)号:US4130865A

    公开(公告)日:1978-12-19

    申请号:US620131

    申请日:1975-10-06

    摘要: Computer apparatus which employs a plurality of processing units, a memory unit, and a communication unit, each of the units including a data transfer bus. A bus coupler is provided between each pair of units of differing type to form a distributed data communications network. An addressable, passive task register is associated with one of the units for communication through the couplers and is adapted to register a task priority value associated with a task request, the register being readable by any one of the processor units to obtain the highest priority value registry.

    摘要翻译: 使用多个处理单元的计算机设备,存储单元和通信单元,每个单元包括数据传输总线。 在不同类型的每对单元之间提供总线耦合器以形成分布式数据通信网络。 可寻址的被动任务寄存器与用于通过耦合器通信的单元之一相关联,并且适于注册与任务请求相关联的任务优先级值,该寄存器可由任何一个处理器单元读取以获得最高优先级值 注册表。

    Error-checking scheme
    2.
    发明授权
    Error-checking scheme 失效
    错误检查方案

    公开(公告)号:US4035766A

    公开(公告)日:1977-07-12

    申请号:US601145

    申请日:1975-08-01

    申请人: William B. Barker

    发明人: William B. Barker

    IPC分类号: G06F11/10 G11C29/00 H04L1/10

    CPC分类号: G06F11/10

    摘要: The error-checking scheme disclosed herein is adapted for use in digital data processing systems, e.g. computers, in which binary data is variously transmitted and/or stored and in which the data source or destination is designated by a binary address. In a preferred embodiment, the data is divided into two fields and a respective parity bit is generated corresponding to each data field. Each data parity bit is then combined with a parity bit corresponding to the binary address to yield a respective combinational parity bit. Each of the resultant combinational parity bits is then sourced with the respective data field. Accordingly, a system sub-component receiving the sourced data with the combinational parity bits can detect any type of single error occurring in either the address or the data.

    摘要翻译: 本文公开的错误检查方案适用于数字数据处理系统,例如, 计算机,其中二进制数据被不同地发送和/或存储,并且数据源或目的地由二进制地址指定。 在优选实施例中,数据被分成两个字段,并且对应于每个数据字段生成相应的奇偶校验位。 然后将每个数据奇偶校验位与对应于二进制地址的奇偶校验位组合,以产生相应的组合奇偶校验位。 所得到的组合奇偶校验位中的每一个然后用相应的数据字段来源。 因此,接收具有组合奇偶校验位的源数据的系统子组件可以检测在地址或数据中发生的任何类型的单个错误。

    NOISE SUPPRESSION FOR DETECTION AND LOCATION OF MICROSEISMIC EVENTS USING A MATCHED FILTER
    3.
    发明申请
    NOISE SUPPRESSION FOR DETECTION AND LOCATION OF MICROSEISMIC EVENTS USING A MATCHED FILTER 审中-公开
    使用匹配过滤器检测和定位微生物活动的噪声抑制

    公开(公告)号:US20090296525A1

    公开(公告)日:2009-12-03

    申请号:US12127205

    申请日:2008-05-27

    IPC分类号: G01V1/36

    CPC分类号: G01V1/366 G01V2210/123

    摘要: A method for determining presence of seismic events in seismic signals includes determining presence of at least one seismic event in seismic signals corresponding to each of a plurality of seismic sensors. A correlation window is selected for each of the plurality of seismic signals. Each correlation window has a selected time interval including an arrival time of the at least one seismic event in each seismic signal. Each window is correlated to the respective seismic signal between a first selected time and a second selected time. Presence of at least one other seismic event in the seismic signals from a result of the correlating.

    摘要翻译: 一种用于确定地震信号中地震事件的存在的方法包括确定至少一个地震事件在与多个地震传感器中的每一个对应的地震信号中的存在。 为多个地震信号中的每一个选择相关窗口。 每个相关窗口具有选定的时间间隔,包括至少一个地震事件在每个地震信号中的到达时间。 每个窗口与第一选定时间和第二选定时间之间的相应地震信号相关。 在地震信号中存在至少一个其他地震事件,从相关的结果。