Data Bus With Multi-Input Pipeline
    1.
    发明申请

    公开(公告)号:US20200348942A1

    公开(公告)日:2020-11-05

    申请号:US16881205

    申请日:2020-05-22

    IPC分类号: G06F9/38 G06F9/30 H01L29/08

    摘要: A data bus includes process elements and a linear main pipeline. Each process element is coupled to a linear pipeline having M stages arranged in series, each of the M stages including a buffer element configured to buffer a data bit sequence and to forward the buffered data bit sequence from a first of the buffer elements to a last of the buffer elements. The linear main pipeline includes N pipeline stage elements arranged in series. Each pipeline stage element is connected to the last buffer element of a respective linear pipeline and configured to read-out one or more of the buffered data bit sequences and to forward the read-out data bit sequences from one of N pipeline stag elements to a next of the N pipeline stage elements.