公开(公告)号：US09385190B2

公开(公告)日：2016-07-05

申请号：US14196278

申请日：2014-03-04

Applicant: Freescale Semiconductor, Inc.

Inventor： John M. Pigott ,  Brent D. Rogers ,  Randall C. Gray

IPC: H01L29/06 ,  H01L23/525 ,  H01L27/06 ,  H01L21/762 ,  H01L27/02

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/76283 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0676 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The embodiments described herein provide a semiconductor device layout and method that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes a plurality of deep trench isolation structures that define and surround a first plurality of first trench-isolated regions in the substrate, and further define a second plurality of second trench-isolated regions in the substrate. The first plurality of first trench-isolated regions is arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions. Likewise, the plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that a second trench-isolated region is between consecutive first columns in the array and such that at least two first trench-isolated regions are between consecutive second trench-isolated regions in the array.

Abstract translation: 本文描述的实施例提供可用于各种各样的半导体器件的半导体器件布局和方法。 在一个实施例中，提供了半导体器件，其包括多个深沟槽隔离结构，其限定并围绕衬底中的第一多个第一沟槽隔离区域，并且还限定衬底中的第二多个第二沟槽隔离区域。 第一多个第一沟槽隔离区域布置在多个第一列中，其中每个第一列包括第一多个第一沟槽隔离区域中的至少两个。 类似地，多个第一列与第二沟槽隔离区交替排列成阵列中的交替，使得第二沟槽隔离区在阵列中连续的第一列之间，使得至少两个第一沟槽隔离区在 阵列中连续的第二沟槽隔离区域。