公开(公告)号：US10324723B2

公开(公告)日：2019-06-18

申请号：US14321957

申请日：2014-07-02

Applicant: Freescale Semiconductor Inc.

Inventor： Peter J Wilson ,  Brian C Kahne ,  Jeffrey W Scott

IPC: G06F9/30 ,  G06F9/35 ,  G06F9/38

Abstract: Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.

公开(公告)号：US10031753B2

公开(公告)日：2018-07-24

申请号：US14719390

申请日：2015-05-22

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Peter J Wilson ,  Brian C Kahne

IPC: G06F9/30 ,  G06F9/38

Abstract: In a pipelined element configured to execute multiple contexts and including an instruction pipeline and a plurality of context modules each having a register file and a functional unit, a method includes scheduling a first context for execution in the instruction pipeline. The instruction pipeline includes an execution unit having a plurality of functional units. Each functional unit of the plurality of functional units is configured to execute instructions of a scheduled context of the plurality of contexts. A first instruction of the first context which precedes an instruction loop of the first context is executed. In response to executing the first instruction, the first context is released from being scheduled for execution in the instruction pipeline and execution of the first context is continued using a first context module. The first context module includes a context-specific functional unit configured to execute the instruction loop.