公开(公告)号：US10324723B2

公开(公告)日：2019-06-18

申请号：US14321957

申请日：2014-07-02

Applicant: Freescale Semiconductor Inc.

Inventor： Peter J Wilson ,  Brian C Kahne ,  Jeffrey W Scott

IPC: G06F9/30 ,  G06F9/35 ,  G06F9/38

Abstract: Disclosed is a digital processor comprising an instruction memory having a first input, a second input, a first output, and a second output. A program counter register is in communication with the first input of the instruction memory. The program counter register is configured to store an address of an instruction to be fetched. A data pointer register is in communication with the second input of the instruction memory. The data pointer register is configured to store an address of a data value in the instruction memory. An instruction buffer is in communication with the first output of the instruction memory. The instruction buffer is arranged to receive an instruction according to a value at the program counter register. A data buffer is in communication with the second output of the instruction memory. The data buffer is arranged to receive a data value according to a value at the data pointer register.