公开(公告)号：US20030120912A1

公开(公告)日：2003-06-26

申请号：US10157992

申请日：2002-05-31

Applicant: Fujitsu Limited

Inventor： Takeo Sasaki ,  Koichi Kuroiwa ,  Shoji Taniguchi ,  Takanobu Kashiwagi

IPC: G06F015/177 ,  G06F001/26

CPC classification number: G06F9/4401

Abstract: A processor and method of booting the processor in which dispensable circuit operation is eliminated to reduce power consumption. A first expected check-sum value relating to instructions and table data and a second expected check-sum value relating only to instructions are held in a boot ROM. When power is turned on, if a power-on determination circuit determines that the power has been turned on for a system, a read selection circuit loads instructions and the table data into an instruction storage memory and a table data storage memory and a check-sum performing circuit performs check-sum using the first expected check-sum value. In the case where the power has been turned on for periodic operation, instructions are loaded into the instruction storage memory, check-sum is performed using the second expected check-sum value, and table data that was saved in a backup memory is loaded into the table data storage memory. Thus, the time required for loading from the boot ROM for the periodic operation decreases.

Abstract translation: 引导处理器的处理器和方法，其中消除了可分配的电路操作以降低功耗。 与指令和表数据相关的第一预期校验和值和仅与指令相关的第二预期校验和值被保存在引导ROM中。 当电源接通时，如果上电确定电路确定系统已经接通电源，则读选择电路将指令和表数据加载到指令存储存储器和表数据存储存储器中， 总和执行电路使用第一预期校验和值来执行校验和。 在电源已经接通周期性操作的情况下，指令被加载到指令存储器中，使用第二预期校验和值进行校验和，并将保存在备用存储器中的表数据加载到 表数据存储内存。 因此，用于周期性操作的从引导ROM加载所需的时间减少。