公开(公告)号：US20030133337A1

公开(公告)日：2003-07-17

申请号：US10300592

申请日：2002-11-21

Applicant: FUJITSU LIMITED

Inventor： Yoshikazu Yamada ,  Koichi Kuroiwa ,  Shoji Taniguchi ,  Takanobu Kashiwagi

IPC: G11C007/00

CPC classification number: H04B1/40 ,  H04W52/028 ,  Y02D70/24 ,  Y02D70/40

Abstract: A proposed semiconductor device is directed to making unnecessary circuit operation inactive to reduce power consumption because of leakage current. The device is functionally divided into blocks. The power supply systems of the blocks are divided into a non-controlled power supply group in which power is always on and controlled power supply groups in each of which groups a supply of power can be turned on/off independently. When a power supply system control part of the non-controlled power supply group outputs a control signal for power on, a power switch part turns on to release the controlled power supply group from the sleep mode, so that the first processing part starts intermittent operation. Only when it is determined that a first next-processing necessity determining part determines necessity of the next processing, a control signal is generated to activate the next power supply group. The blocks unnecessary for processing are not supplied with power, so that no leakage current flows and power consumption because thereof can be reduced.

Abstract translation: 所提出的半导体器件旨在使不必要的电路操作无效以便由于泄漏电流而降低功耗。 该设备在功能上划分为块。 块的电源系统分为电源始终接通的非受控电源组，每个组中的电源组可独立接通/断开。 当非受控电源组的电源系统控制部分输出用于接通电源的控制信号时，电源开关部分接通以将受控电源组从睡眠模式释放，使得第一处理部分开始间歇操作 。 只有当确定第一下一个处理必要性确定部分确定下一个处理的必要性时，才产生控制信号以激活下一个电源组。 不需要处理的块被供电，所以不会有泄漏电流流动，因此可以减少功耗。

公开(公告)号：US20030146462A1

公开(公告)日：2003-08-07

申请号：US10346103

申请日：2003-01-17

Applicant: FUJITSU LIMITED

Inventor： Jun Iwata ,  Shoji Taniguchi ,  Koichi Kuroiwa ,  Yoshikazu Yamada

IPC: H01L027/108 ,  H01L029/04 ,  H01L029/76

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  H04W52/028 ,  Y02D10/171 ,  Y02D70/24

Abstract: A semiconductor device that quickly saves data stored in an area to which power is supplied intermittently. Power is supplied intermittently to a first area. Power is supplied continuously to a second area. A memory is located in the second area. A save circuit saves data used in the first area in the memory before the supply of power being stopped. A restoration circuit restores data which has been saved in the memory to a predetermined circuit in the first area. A power supply control circuit supplies power to the memory if data has been saved in the memory. Otherwise the power supply control circuit stops the supply of power to the memory.

Abstract translation: 一种半导体器件，其能够快速地保存间歇地供电的区域中存储的数据。 间歇地供电到第一区域。 电源连续供应到第二个区域。 内存位于第二区。 节电电路在电源供电停止之前，将存储器中第一个区域中使用的数据保存在存储器中。 恢复电路将保存在存储器中的数据恢复到第一区域中的预定电路。 如果数据已被保存在存储器中，则电源控制电路向存储器供电。 否则电源控制电路停止向存储器供电。

公开(公告)号：US20030042972A1

公开(公告)日：2003-03-06

申请号：US10097619

申请日：2002-03-15

Applicant: FUJITSU LIMITED

Inventor： Yoshikazu Yamada ,  Masami Kanasugi ,  Shoji Taniguchi ,  Koichi Kuroiwa

IPC: G05F001/10

CPC classification number: G06F1/3237 ,  G06F1/3203 ,  Y02D10/128

Abstract: A semiconductor integrated circuit includes a plurality of functional blocks, each of which starts and stops an operation thereof in response to assertion and negation, respectively, of a corresponding command signal, a clock generation circuit which generates a clock signal, a clock control circuit which starts supplying the clock signal to each of the functional blocks in response to the assertion of the corresponding command signal, and stops supplying the clock signal to each of the functional blocks in response to the negation of the corresponding command signal.

公开(公告)号：US20030146856A1

公开(公告)日：2003-08-07

申请号：US10342094

申请日：2003-01-15

Applicant: FUJITSU LIMITED

Inventor： Norihiro Ikeda ,  Shoji Taniguchi ,  Masami Kanasugi ,  Koichi Kuroiwa

IPC: H03M007/00

CPC classification number: H04J13/10

Abstract: In a code generation device for generating a code: a binary-data generation circuit generates first binary data items indicating every (mnull1)th one of n successive binary numbers, where mnull1 and nnull2. A binary-data derivation circuit derives mnull1 second binary data items indicating mnull1 binary numbers from each of the first binary data items, where the mnull1 binary numbers include the first binary data item. A first processing circuit performs a predetermined common operation on identical portions of the mnull1 second binary data items, and a second processing circuit performs individually predetermined operations on non-identical portions of the mnull1 second binary data items, where states of corresponding bits in the non-identical portions of the mnull1 second binary data items are not identical. A combining circuit combines the outputs of the first and second processing circuits.

Abstract translation: 在用于生成代码的代码生成装置中，二进制数据生成电路生成表示n个连续的二进制数的每个（m + 1）个的第二个二进制数据项，其中m≥1且n> = 2。 二进制数据导出电路从每个第一二进制数据项导出指示m + 1个二进制数的m + 1秒二进制数据项，其中m + 1个二进制数包括第一个二进制数据项。 第一处理电路对m + 1个第二二进制数据项的相同部分执行预定的公共操作，第二处理电路对m + 1个第二二进制数据项的不相同部分执行单独预定的操作，其中相应的 m + 1个第二二进制数据项的不相同部分中的位不相同。 组合电路组合第一和第二处理电路的输出。

公开(公告)号：US20030050022A1

公开(公告)日：2003-03-13

申请号：US10102738

申请日：2002-03-22

Applicant: Fujitsu Limited

Inventor： Koichi Kuroiwa ,  Shoji Taniguchi ,  Masami Kanasugi ,  Junichi Sugimoto

IPC: H04B017/02

CPC classification number: H04B1/70754 ,  H04B2201/70701 ,  H04B2201/70702 ,  H04B2201/7071

Abstract: A receiving unit that reduces the amount of power consumed for detecting the timing of each of a plurality of paths via which received signals were received. A receiving section receives signals sent from a base station and transmitted via a plurality of paths. A path detecting section detects the timing of each of the plurality of paths via which the received signals received by the receiving section were transmitted. A path detection range setting section sets a range where a path is detected by the path detecting section on the basis of information indicative of path timing detected by the path detecting section.

Abstract translation: 接收单元，其减少用于检测接收到的信号的多个路径中的每一个的定时的消耗的功率量。 接收部分接收从基站发送并经由多个路径发送的信号。 路径检测部分检测由接收部分接收的接收信号经由哪个多个路径中的每一个的定时被发送。 路径检测范围设定部根据由路径检测部检测到的路径定时的信息，设定由路径检测部检测出路径的范围。

公开(公告)号：US20030026328A1

公开(公告)日：2003-02-06

申请号：US10102814

申请日：2002-03-22

Applicant: Fujitsu Limited

Inventor： Yoshikazu Yamada ,  Shoji Taniguchi ,  Koichi Kuroiwa ,  Masami Kanasugi

IPC: H04K001/00

CPC classification number: H04B1/7113 ,  H04B2201/7071

Abstract: A receiving unit, receiving method, and semiconductor device that reduce the size of circuits in a receiving unit. A receiving section receives signals sent from a base station and transmitted through a plurality of paths. A path tracking section detects timing of each of the plurality of paths through which the signals received by the receiving section were transmitted. A demodulating section demodulates the received signals by performing a despreading process according to the timing of the plurality of paths detected by the path tracking section. A correlation value calculating section calculates a correlation value between the received signals and a spreading code. A destination selecting section provides output from the correlation value calculating section to the path tracking section in the case of performing a path tracking process by the path tracking section and provides output from the correlation value calculating section to the demodulating section in the case of demodulating the received signals by the demodulating section.

Abstract translation: 一种减小接收单元中的电路尺寸的接收单元，接收方法和半导体器件。 接收部分接收从基站发送并通过多个路径发送的信号。 路径跟踪部分检测发送由接收部分接收的信号的多个路径中的每一个的定时。 解调部通过根据由路径追踪部检测出的多个路径的定时进行解扩处理来解调接收信号。 相关值计算部分计算接收信号和扩展码之间的相关值。 目的地选择部分在路径跟踪部分执行路径跟踪处理的情况下，将相关值计算部分的输出提供给路径跟踪部分，并且在解调该解调部分的情况下将相关值计算部分的输出提供给解调部分 由解调部分接收信号。

公开(公告)号：US20030120912A1

公开(公告)日：2003-06-26

申请号：US10157992

申请日：2002-05-31

Applicant: Fujitsu Limited

Inventor： Takeo Sasaki ,  Koichi Kuroiwa ,  Shoji Taniguchi ,  Takanobu Kashiwagi

IPC: G06F015/177 ,  G06F001/26

CPC classification number: G06F9/4401

Abstract: A processor and method of booting the processor in which dispensable circuit operation is eliminated to reduce power consumption. A first expected check-sum value relating to instructions and table data and a second expected check-sum value relating only to instructions are held in a boot ROM. When power is turned on, if a power-on determination circuit determines that the power has been turned on for a system, a read selection circuit loads instructions and the table data into an instruction storage memory and a table data storage memory and a check-sum performing circuit performs check-sum using the first expected check-sum value. In the case where the power has been turned on for periodic operation, instructions are loaded into the instruction storage memory, check-sum is performed using the second expected check-sum value, and table data that was saved in a backup memory is loaded into the table data storage memory. Thus, the time required for loading from the boot ROM for the periodic operation decreases.

Abstract translation: 引导处理器的处理器和方法，其中消除了可分配的电路操作以降低功耗。 与指令和表数据相关的第一预期校验和值和仅与指令相关的第二预期校验和值被保存在引导ROM中。 当电源接通时，如果上电确定电路确定系统已经接通电源，则读选择电路将指令和表数据加载到指令存储存储器和表数据存储存储器中， 总和执行电路使用第一预期校验和值来执行校验和。 在电源已经接通周期性操作的情况下，指令被加载到指令存储器中，使用第二预期校验和值进行校验和，并将保存在备用存储器中的表数据加载到 表数据存储内存。 因此，用于周期性操作的从引导ROM加载所需的时间减少。

公开(公告)号：US20030115507A1

公开(公告)日：2003-06-19

申请号：US10223468

申请日：2002-08-20

Applicant: Fujitsu Limited

Inventor： Koichi Kuroiwa ,  Shoji Taniguchi ,  Masami Kanasugi

IPC: H04L001/22

CPC classification number: H04W52/0229 ,  Y02D70/24

Abstract: A semiconductor device in which consumption of power attendant on a leakage current in a block where the power is turned on and off intermittently is reduced. In the semiconductor device according to the present invention, an error check necessity judgment circuit judges on notification from an error check necessity notification circuit located in a block where the power is not disconnected whether an error check must be made, and an error check execution circuit makes an error check on data loaded from an external memory at the time of a boot in accordance with the judgment of the error check necessity judgment circuit. An error check cannot completely be omitted. Therefore, to ensure the reliability of a system, an error check is forcedly made once whenever a boot is performed times set by an error check interval setting circuit. This shortens intermittent operation time by time taken to make an error check, resulting in a reduction in consumption of power attendant on a useless leakage current.

Abstract translation: 间歇地断开电源的块中的泄漏电流的电力消耗减少的半导体装置。 在根据本发明的半导体器件中，错误检查必要性判断电路根据来自位于不断开的块中的错误检查必要性通知电路的通知来判断是否必须进行错误检查，以及错误检查执行电路 根据错误检查必要性判断电路的判断，在引导时对来自外部存储器的数据进行错误检查。 错误检查不能完全省略。 因此，为了确保系统的可靠性，每当由错误检查间隔设置电路设置引导时间时，强制进行错误检查。 这缩短了间歇操作时间，以便进行错误检查所花费的时间，从而在无用的漏电流下降低功率消耗。

公开(公告)号：US20030067965A1

公开(公告)日：2003-04-10

申请号：US10105191

申请日：2002-03-26

Applicant: FUJITSU LIMITED of KAWASAKI, JAPAN

Inventor： Shoji Taniguchi ,  Koichi Kuroiwa ,  Masami Kanasugi ,  Yoshikazu Yamada ,  Mahiro Hikita

IPC: H04K001/00

CPC classification number: H04B1/7115 ,  H04B1/712

Abstract: A receiving unit for receiving a CDMA system signal having a plurality of multipath components is intended to reduce the size. A receiving section receives a CDMA system signal. A storage section stores the signal received by the receiving section. A demodulation section demodulates each of multipath components included in the received signal stored in the storage section with a despreading code. A control section controls for demodulating a plurality of the multipath components by causing the demodulation section to perform a time division multiplex process. A Rake combining section performs the maximal ratio combining of output from the demodulation section to generate a demodulated signal.

Abstract translation: 用于接收具有多个多径分量的CDMA系统信号的接收单元旨在减小尺寸。 接收部分接收CDMA系统信号。 存储部存储由接收部接收的信号。 解调部分用解扩码解调包含在存储部分中的接收信号中的每个多径分量。 控制部分通过使解调部分进行时分复用处理来控制多个多径分量的解调。 Rake组合部分执行来自解调部分的输出的最大比组合以产生解调信号。

公开(公告)号：US20030046636A1

公开(公告)日：2003-03-06

申请号：US10223216

申请日：2002-08-20

Applicant: Fujitsu Limited

Inventor： Masami Kanasugi ,  Shoji Taniguchi ,  Koichi Kuroiwa ,  Mahiro Hikita

IPC: H03M013/00

CPC classification number: H03M13/091 ,  H03M13/09 ,  H03M13/23 ,  H03M13/39 ,  H03M13/41

Abstract: An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string. The reception bit string is inputted to the first feedback shift register in the same order in which the transmission bit string was generated, while the reception bit string is inputted to the second feedback shift register in reverse order to one which the transmission bit string was generated. Errors in the reception bit string are detected by comparing respective remainders obtained by the first and second feedback shift registers. This reduces the processing time required for the error detection and increases efficiency in detecting errors in transmitted data.

Abstract translation: 接收机的误差检测器包括反馈移位寄存器。 反馈移位寄存器中的移位方向与通过使用指定的生成多项式生成传输位串时的发送器处的移位方向相反。 接收比特串以相反的顺序输入到反馈移位寄存器，在发送器处产生发送比特串，从而通过获得余数来检测接收比特串中的错误。 接收机处的另一个误差检测器包括第一和第二反馈移位寄存器。 第一和第二反馈移位寄存器中的相应移位方向与发送器在生成传输位串时的移位方向相同且相反。 接收比特串以与生成发送比特串相同的顺序输入到第一反馈移位寄存器，而接收比特串以相反的顺序被输入到第二反馈移位寄存器，以产生发送比特串 。 通过比较由第一和第二反馈移位寄存器获得的各个余数来检测接收位串中的错误。 这减少了错误检测所需的处理时间，并提高了检测传输数据中错误的效率。