公开(公告)号：US20020008323A1

公开(公告)日：2002-01-24

申请号：US09735479

申请日：2000-12-14

申请人： Fujitsu Limited, Kawasaki, Japan

发明人： Kenichi Watanabe ,  Daisuke Komada ,  Fumihiko Shimpuku

IPC分类号： H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC分类号： H01L21/76808 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76829 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer. The semiconductor device is provided which can protect the underlying conductive region sufficiently and has a dual damascene wiring layer having a high reliability and a small wiring capacitance.

摘要翻译： 一种半导体器件，具有：在基底的表层中具有导电区域的基底; 覆盖基底表面的绝缘蚀刻阻挡膜; 形成在所述绝缘蚀刻停止膜上的层间绝缘膜; 形成在所述层间绝缘膜中的布线沟槽，所述布线沟槽具有从所述层间绝缘膜的表面的第一深度; 从所述布线沟槽的底表面延伸到所述导电区域的表面的接触孔; 以及嵌入在所述布线沟槽和所述接触孔中的双镶嵌布线层，其中所述层间绝缘膜包括围绕所述布线沟槽的侧壁和底面的第一种绝缘层和具有蚀刻的第二种绝缘层 特性不同于第一种绝缘层。 提供了可以充分保护下面的导电区域并具有高可靠性和小布线电容的双镶嵌布线层的半导体器件。