公开(公告)号：US20040256717A1

公开(公告)日：2004-12-23

申请号：US10835824

申请日：2004-04-30

发明人： Hiroshi Suenaga ,  Yoshiyuki Saito

IPC分类号： H01L023/52 ,  H01L023/48

CPC分类号： H01L23/50 ,  H01L23/49822 ,  H01L23/5389 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/185 ,  H01L2224/05599

摘要： According to LSI packages of the BGA type and the like, the number of source voltage supply terminals on an LSI package needs to be around the same as the number of power supply terminals on an LSI chip, in order to prevent the impact of high-frequency currents generated due to a switching operation in an internal circuit in the LSI chip. According to the present invention, however, at least two power supply terminals on an LSI chip are connected to one source voltage supply terminal on an LSI package. In addition, a capacitor element is embedded in a substrate forming the main body of the LSI package, and the capacitor element is provided between a source voltage supply terminal and an earth terminal.

摘要翻译： 根据BGA型等的LSI封装，LSI封装上的源极电压供给端子的数量需要与LSI芯片上的电源端子的数量大致相同，以防止高压电池的影响， 由于LSI芯片的内部电路的开关动作而产生的高频电流。 然而，根据本发明，LSI芯片上的至少两个电源端子连接到LSI封装上的一个源极电压端子。 另外，在构成LSI封装的主体的基板中嵌入电容器元件，电容器元件设置在源极电压端子与接地端子之间。

公开(公告)号：US20040251534A1

公开(公告)日：2004-12-16

申请号：US10710731

申请日：2004-07-30

发明人： Nai-Shung Chang ,  Tsai-Sheng Chen ,  Shu-Hui Chen

IPC分类号： H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/119 ,  H01L031/113 ,  H01L023/52

CPC分类号： H05K1/0295 ,  H05K1/0298 ,  H05K1/18 ,  H05K2201/09345 ,  H05K2201/09954 ,  H05K2201/10522 ,  H05K2201/10704 ,  H05K2201/10734

摘要： A layout structure of a central processing unit (CPU) that supports two different package techniques, comprising a motherboard that comprises the layout structure and a layout method. The layout structure of the preferred embodiment according to the present invention from up to down sequentially places a top signal layer, a grounded layer, a power layer having a grounded potential, and a bottom solder layer in the area where the signals of the CPU are coupled to the signals of the control chip, so that the signals that are placed on the bottom solder layer can refer to a grounded potential area of the power layer. Therefore, part of signals of the CPU that are coupled to the control chip can be placed on the bottom solder layer. Since the preferred embodiment of the present invention provides more flexibility in the placement design, a layout structure that supports the Pentium IV CPUs of different package techniques can be designed on the motherboard of the 4 layers stack structure, and these two CPUs can be supported by the same control chip.

摘要翻译： 支持两种不同包装技术的中央处理单元（CPU）的布局结构，包括包括布局结构和布局方法的主板。 根据本发明的优选实施例的布局结构从上到下顺序地在CPU的信号区域中放置顶层信号层，接地层，具有接地电位的功率层和底部焊料层 耦合到控制芯片的信号，使得放置在底部焊料层上的信号可以指功率层的接地电位区域。 因此，耦合到控制芯片的CPU的部分信号可以放置在底部焊料层上。 由于本发明的优选实施例在布局设计中提供了更多的灵活性，因此可以在四层堆栈结构的主板上设计支持不同封装技术的Pentium IV CPU的布局结构，并且这两个CPU可以被 相同的控制芯片。

公开(公告)号：US20040245631A1

公开(公告)日：2004-12-09

申请号：US10453157

申请日：2003-06-03

申请人： Micrel, Incorporated

发明人： Martin Alter

IPC分类号： H01L023/48 ,  H01L023/52

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/13099 ,  H01L2224/24137 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599

摘要： Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described.

摘要翻译： 作为集成电路结构的一部分，晶片级芯片级封装技术用于通过使用焊盘到凸出光束的金属化来提高集成电路的性能或减小尺寸。 芯片级封装凸块下的金属被布线以增加集成电路的顶部金属的厚度，增加载流能力和降低电阻。 描述了功率MOSFET阵列集成结构的示例性实施例。

公开(公告)号：US20040245620A1

公开(公告)日：2004-12-09

申请号：US10454656

申请日：2003-06-03

发明人： Jackson Hsieh ,  Jichen Wu ,  Worrell Tsai

IPC分类号： H01L023/52

CPC分类号： H01L23/544 ,  H01L2223/54473 ,  H01L2924/0002 ,  H05K1/0266 ,  H05K1/117 ,  H05K2201/094 ,  H01L2924/00

摘要： A memory card for being electrically connected to an electrical device. The memory card includes a substrate, and at least one memory chip. The substrate is formed with a plurality of contact leads, which is electrically connected to the electrical device when the substrate is inserted into the electrical device. The plurality of contact leads includes a long contact lead and a short contact lead to indicate an inserting direction of the substrate into the electrical device. The memory chip is mounted to the substrate and electrically connected to the plurality of contact leads.

摘要翻译： 一种用于电连接到电气设备的存储卡。 存储卡包括基板和至少一个存储芯片。 基板形成有多个接触引线，当基板插入电气设备时，该接触引线电连接到电气设备。 多个接触引线包括长接触引线和短接触引线，以指示基板插入电气装置的插入方向。 存储器芯片安装到基板并电连接到多个接触引线。

公开(公告)号：US20040245617A1

公开(公告)日：2004-12-09

申请号：US10839303

申请日：2004-05-05

申请人： Tessera, Inc.

发明人： Philip Damberg ,  Ilyas Mohammed

IPC分类号： H01L021/48 ,  H01L023/52

CPC分类号： H01L25/18 ,  H01L25/0652 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A memory chip module includes multiple stacks of memory chips arranged on a base panel. The chip stacks desirably are arranged in rows symmetrical about a central plane and define a channel in a central region of the base panel. Control chips such as a register chip associated with the memory chips in the stacks can be provided in this central region of the base panel. Desirably, the base panel is surface-mountable on a circuit board. The module provides high memory chip packing density, effective cooling and short, balanced signal lines between the control chip and the memory chip stacks.

摘要翻译： 存储芯片模块包括布置在基板上的多个存储芯片堆叠。 芯片堆叠期望地布置成围绕中心平面对称的行并且在基板的中心区域中限定通道。 诸如与堆叠中的存储器芯片相关联的寄存器芯片的控制芯片可以设置在基板的该中心区域中。 理想地，基板可以表面安装在电路板上。 该模块在控制芯片和存储芯片堆栈之间提供高存储器芯片封装密度，有效冷却和短路平衡信号线。

公开(公告)号：US20040245548A1

公开(公告)日：2004-12-09

申请号：US10821290

申请日：2004-04-09

申请人： SEMIKRON Elektronik GmbH

发明人： Thomas Stockmeier ,  Jurgen Steger

IPC分类号： H01L023/52

CPC分类号： H01L23/3735 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L25/072 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19107 ,  H05K1/144 ,  H05K3/325 ,  H01L2924/05432 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A power semiconductor module has a base plate comprising a framelike housing, a cap, and at least one electrically insulated substrate disposed inside the housing. The substrate comprises an insulation body with a plurality of metal connection tracks located thereon and insulated from one another, power semiconductor components located on the connection tracks, and terminal elements leading to the outside of the power semiconductor module for load and auxiliary contacts. Some of these terminal elements in the interior of the power semiconductor module comprise contact springs, which are disposed between the connection tracks and contact points on a printed circuit board. The printed circuit board has conductor tracks, which connect the contact points to contact elements that lead to the outside of the power semiconductor module.

摘要翻译： 功率半导体模块具有基板，该基板包括框架壳体，盖子，以及设置在壳体内部的至少一个电绝缘基板。 基板包括绝缘体，其具有位于其上并彼此绝缘的多个金属连接轨道，位于连接轨道上的功率半导体部件以及通向用于负载和辅助触点的功率半导体模块外部的端子元件。 功率半导体模块内部的这些端子元件中的一些包括接触弹簧，其设置在印刷电路板上的连接轨道和接触点之间。 印刷电路板具有导体轨道，其将接触点连接到通向功率半导体模块外部的接触元件。

公开(公告)号：US20040227252A1

公开(公告)日：2004-11-18

申请号：US10809384

申请日：2004-03-26

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Sung-Fei Wang

IPC分类号： H01L023/52

CPC分类号： H01L21/563 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401

摘要： A flip chip package comprises a substrate, a chip, a plurality of electrically conductive bumps and reinforced bumps. The chip has an active surface having a central area and a peripheral area surrounding the central region. The electrically conductive bumps are disposed at the peripheral region of the chip to electrically connect to the substrate. In addition, the reinforced bumps are disposed at the central area of the chip. In such manner, it can enhance the connection between the chip and the substrate.

摘要翻译： 倒装芯片封装包括衬底，芯片，多个导电凸块和加强的凸块。 芯片具有中心区域和围绕中央区域的周边区域的活性表面。 导电凸块设置在芯片的周边区域以电连接到基板。 此外，加强凸块设置在芯片的中心区域。 以这种方式，它可以增强芯片和衬底之间的连接。

公开(公告)号：US20040207090A1

公开(公告)日：2004-10-21

申请号：US10842455

申请日：2004-05-11

发明人： Paul A. Farrar

IPC分类号： H01R012/04 ,  H05K001/11 ,  H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC分类号： H01L23/522 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and extending in the same direction. One embodiment may further include a larger than normal insulator material between planes of wiring extending in one direction and at least one plane of wiring extending in a second direction transverse to the first direction. Each of the wiring channels in a wiring plane may be offset relative to a respective wiring channel in the next adjacent wiring plane which extends in the same direction.

公开(公告)号：US20040188823A1

公开(公告)日：2004-09-30

申请号：US10709012

申请日：2004-04-07

申请人： International Business Machines Corporation

发明人： Glenn G. Daves ,  Jason Frankel ,  William F. Shutler ,  Anthony Wayne Sigler ,  Herbert I. Stoller ,  John Vetrero ,  Cathy Ann Zadany

IPC分类号： H01L023/48 ,  H01L023/52 ,  H05K001/11 ,  H05K001/14

CPC分类号： H01L24/17 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H05K1/0289 ,  H05K1/112

摘要： A jogging structure for translating wiring connections from points in a first grid to corresponding points in a second grid in a chip carrier module is disclosed. In an exemplary embodiment, the structure includes a first translation layer, coupled to the first grid, the first translation layer translating the first grid in an x-axis direction. A second translation layer is coupled to the first translation layer, the second translation layer for translating said wiring connections from the first grid in a y-axis direction, the y-axis direction being orthogonal to the x-axis direction. The second translation layer is further coupled to the second grid.

摘要翻译： 公开了一种用于将布线连接从第一网格中的点转换到芯片载体模块中的第二网格中的相应点的慢跑结构。 在示例性实施例中，该结构包括耦合到第一格栅的第一平移层，第一平移层沿x轴方向平移第一格栅。 第二平移层耦合到第一平移层，第二平移层用于在y轴方向上从第一栅格平移所述布线连接，y轴方向与x轴方向正交。 第二平移层还耦合到第二栅极。

公开(公告)号：US20040180486A1

公开(公告)日：2004-09-16

申请号：US10804039

申请日：2004-03-19

申请人： SEIKO EPSON CORPORATION

发明人： Nobuaki Hashimoto

IPC分类号： H01L023/52

CPC分类号： H01L24/16 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/14131 ,  H01L2224/16 ,  H01L2224/73104 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00

摘要： A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of providing a resin layer (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); a step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal thin film fabrication technology is used during the wafer process.