公开(公告)号：US10929136B2

公开(公告)日：2021-02-23

申请号：US15950434

申请日：2018-04-11

Applicant: Futurewei Technologies, Inc.

Inventor： Shiwen Hu ,  Wei Yu Chen ,  Michael Chow ,  Qian Wang ,  Yongbin Zhou ,  Lixia Yang ,  Ning Yang

IPC: G06F9/38

Abstract: Branch prediction techniques are described that can improve the performance of pipelined microprocessors. A microprocessor with a hierarchical branch prediction structure is presented. The hierarchy of branch predictors includes: a multi-cycle predictor that provides very accurate branch predictions, but with a latency of multiple cycles; a small and simple branch predictor that can provide branch predictions for a sub-set of instructions with zero-cycle latency; and a fast, intermediate level branch predictor that provides relatively accurate branch prediction, while still having a low, but non-zero instruction prediction latency of only one cycle, for example. To improve operation, the higher accuracy, higher latency branch direction predictor and the fast, lower latency branch direction predictor can share a common target predictor.

公开(公告)号：US20190317769A1

公开(公告)日：2019-10-17

申请号：US15950434

申请日：2018-04-11

Applicant: Futurewei Technologies, Inc.

Inventor： Shiwen Hu ,  Wei Yu Chen ,  Michael Chow ,  Qian Wang ,  Yongbin Zhou ,  Lixia Yang ,  Ning Yang

IPC: G06F9/38

Abstract: Branch prediction techniques are described that can improve the performance of pipelined microprocessors. A microprocessor with a hierarchical branch prediction structure is presented. The hierarchy of branch predictors includes: a multi-cycle predictor that provides very accurate branch predictions, but with a latency of multiple cycles; a small and simple branch predictor that can provide branch predictions for a sub-set of instructions with zero-cycle latency; and a fast, intermediate level branch predictor that provides relatively accurate branch prediction, while still having a low, but non-zero instruction prediction latency of only one cycle, for example. To improve operation, the higher accuracy, higher latency branch direction predictor and the fast, lower latency branch direction predictor can share a common target predictor.

公开(公告)号：US20170090922A1

公开(公告)日：2017-03-30

申请号：US14871229

申请日：2015-09-30

Applicant: Futurewei Technologies, Inc.

Inventor： Jiajin Tu ,  Michael Chow ,  Yongxiang Liang ,  Yongzheng Hao ,  Xiaoyu Wang ,  Jiamin Zheng ,  Shilei Liao

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/3814 ,  G06F9/3853 ,  G06F9/3875

Abstract: A method implemented by a central processing unit (CPU), comprising decoding a first instruction word of a first instruction pair, wherein the first instruction word comprises a first operation code identifying a first operation, storing the first operation code in a register memory upon decoding the first instruction word, decoding a second instruction word of the first instruction pair, wherein the second instruction word comprises a first operand, generating a first decoded instruction pair by combining the first operation code stored in the register memory with the first operand in the second instruction word. The method further comprises executing the first decoded instruction pair by performing the first operation on the first operand.