公开(公告)号：US10929136B2

公开(公告)日：2021-02-23

申请号：US15950434

申请日：2018-04-11

Applicant: Futurewei Technologies, Inc.

Inventor： Shiwen Hu ,  Wei Yu Chen ,  Michael Chow ,  Qian Wang ,  Yongbin Zhou ,  Lixia Yang ,  Ning Yang

IPC: G06F9/38

Abstract: Branch prediction techniques are described that can improve the performance of pipelined microprocessors. A microprocessor with a hierarchical branch prediction structure is presented. The hierarchy of branch predictors includes: a multi-cycle predictor that provides very accurate branch predictions, but with a latency of multiple cycles; a small and simple branch predictor that can provide branch predictions for a sub-set of instructions with zero-cycle latency; and a fast, intermediate level branch predictor that provides relatively accurate branch prediction, while still having a low, but non-zero instruction prediction latency of only one cycle, for example. To improve operation, the higher accuracy, higher latency branch direction predictor and the fast, lower latency branch direction predictor can share a common target predictor.

公开(公告)号：US20190317769A1

公开(公告)日：2019-10-17

申请号：US15950434

申请日：2018-04-11

Applicant: Futurewei Technologies, Inc.

Inventor： Shiwen Hu ,  Wei Yu Chen ,  Michael Chow ,  Qian Wang ,  Yongbin Zhou ,  Lixia Yang ,  Ning Yang

IPC: G06F9/38

Abstract: Branch prediction techniques are described that can improve the performance of pipelined microprocessors. A microprocessor with a hierarchical branch prediction structure is presented. The hierarchy of branch predictors includes: a multi-cycle predictor that provides very accurate branch predictions, but with a latency of multiple cycles; a small and simple branch predictor that can provide branch predictions for a sub-set of instructions with zero-cycle latency; and a fast, intermediate level branch predictor that provides relatively accurate branch prediction, while still having a low, but non-zero instruction prediction latency of only one cycle, for example. To improve operation, the higher accuracy, higher latency branch direction predictor and the fast, lower latency branch direction predictor can share a common target predictor.

公开(公告)号：US20200042322A1

公开(公告)日：2020-02-06

申请号：US16054413

申请日：2018-08-03

Applicant: Futurewei Technologies, Inc.

Inventor： Qian Wang ,  Xiaohan Ma ,  Xingyu Jiang

IPC: G06F9/38 ,  G06F9/30

Abstract: The disclosure relates to technology executing store and load instructions in a processor. Instructions are fetched, decoded and renamed. When a store instruction is fetched, the instruction is cracked into two operation codes in which a first operation code is a store address and a second operation code is a store data. When a fusion condition is detected, the second operation code is fused or merged with an arithmetic operation instruction for which a source register of a store instruction matches a destination register of the arithmetic operation instruction. The first operation code is then dispatched/issued to a first issue queue and the second operation code, fused with the arithmetic operation instruction, is dispatched/issued to a second issue queue.