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    Direct feed rate control circuit
    1.
    发明授权
    Direct feed rate control circuit 失效
    直接进给速率控制电路

    公开(公告)号：US3657525A

    公开(公告)日：1972-04-18

    申请号：US3657525D

    申请日：1970-03-17

    Applicant: GEN ELECTRIC

    Inventor： EVANS JOHN T

    IPC: G05B19/416 ,  G05B19/14 ,  H02P7/42

    CPC classification number: G05B19/416 ,  G05B2219/43189

    Abstract: Control of the rate of motion is provided for a numerical control system utilizing a direct feed rate form of programming. Command pulse trains produced for each axis of motion and a velocity command pulse train representing the programmed velocity of the resultant path of motion are applied to a circuit which indicates a difference resulting from subtracting the sum of the squares of the number of pulses in the individual axis command pulse trains from the sum of the square of the number of pulses in the velocity pulse train over a period of time. The difference is used to control the rate of generation of the axis pulse trains so as to approach zero difference.

    Abstract translation: 为使用直接进给速率形式的编程的数控系统提供对运动速率的控制。 对于每个运动轴产生的指令脉冲串和表示所得运动路径的编程速度的速度指令脉冲串被施加到指示由减去个体中脉冲数的平方和得到的差的电路 轴指令脉冲从一段时间内的速度脉冲串中的脉冲数的平方和之和。 该差异用于控制轴脉冲串的产生速率以接近零差。

    Readout system for visually displaying stored data
    2.
    发明授权
    Readout system for visually displaying stored data 失效
    用于可视显示存储数据的读出系统

    公开(公告)号：US3651481A

    公开(公告)日：1972-03-21

    申请号：US3651481D

    申请日：1968-02-29

    Applicant: GEN ELECTRIC

    Inventor： EVANS JOHN T ,  KELLING LEROY U C

    IPC: G05B19/4069 ,  G09G3/04 ,  G06F7/30 ,  G06F13/02

    CPC classification number: G05B19/4069 ,  G05B2219/34239 ,  G05B2219/35481 ,  G09G3/04

    Abstract: A system for visually displaying interlaced data stored in a recirculating delay line. The stored data is in six functions, each function comprising three eight digit words. Data within each function is interlaced by presenting the least significant digit of all three words, followed by the next to least significant digit of all three words and so on. The data display may be single selected words or may comprise display of particular words in predetermined sequence. Sequential display of all three words in selected functions is accomplished by providing a three bit recirculating shift register. The sequencing rate is controlled by a variable frequency oscillator. It is also possible to sequentially select the data associated with each letter address. This is accomplished by way of a second recirculating shift register whose sequencing rate is also controlled by the variable frequency oscillator. As the data is selected, it is fed into a third shift register where it is stored in binary coded decimal. A BCD to decimal converter converts the contents of the third shift register to decimal format. THe output of the BCD to decimal converter feeds the display device. The rate at which the contents of the third shift register are ''''updated'''' may also be controlled by providing an oscillator whose frequency determines the ''''update'''' rate.

    Abstract translation: 用于可视地显示存储在再循环延迟线中的隔行扫描数据的系统。 存储的数据有六个功能，每个功能包括三个八位数字。 每个功能中的数据通过呈现所有三个字的最低有效数字，随后是所有三个字的下一个最低有效数字，以此类推。 数据显示可以是单个选择的单词，或者可以包括以预定顺序显示特定单词。 通过提供三位循环移位寄存器来实现所选功能中所有三个字的顺序显示。 排序速率由可变频率振荡器控制。 也可以顺序地选择与每个字母地址相关联的数据。 这通过第二再循环移位寄存器来实现，其排序率也由可变频率振荡器控制。 当数据被选择时，它被馈送到第三移位寄存器，其中以二进制编码十进制存储。 BCD到十进制转换器将第三移位寄存器的内容转换为十进制格式。 BCD到十进制转换器的输出为显示设备供电。 也可以通过提供频率确定“更新”速率的振荡器来控制第三移位寄存器的内容“更新”的速率。

    Serial bcd adder/subtracter/complementer utilizing interlaced data
    4.
    发明授权
    Serial bcd adder/subtracter/complementer utilizing interlaced data 失效
    串行BCD ADDER / SUBTRACTER / COMPLEMENTER使用相互连接的数据

    公开(公告)号：US3584206A

    公开(公告)日：1971-06-08

    申请号：US3584206D

    申请日：1968-02-29

    Applicant: GEN ELECTRIC

    Inventor： EVANS JOHN T

    IPC: B65G51/04 ,  G06F7/495 ,  G06F7/50 ,  G11C21/00

    CPC classification number: G06F7/495 ,  B65G51/04 ,  G11C21/00

    Abstract: A serial digital adder/subtracter/complementer for binary coded decimal data presented in interlaced format. The data at each input comprises a series of multidigit decimal words interlaced by serially presenting the least significant digit of each word in predetermined sequence, followed by the next digit of each word similarly interlaced and so on throughout the data. The adder/subtracter/complementer utilizes a first full adder/subtracter for adding or subtracting the input data. The system allows selection of either addition or subtraction and, when subtracting, designates the minuend and subtrahend. The output of the first full adder is passed through three bits of delay to one input of a second full adder/subtracter. As each digit is manipulated, it is examined to see if an incorrect result, i.e., a sum in excess of nine or a negative difference has been generated. If so, the number six (6) in binary coded decimal is fed to a second input of the second adder/subtracter where it is added to or subtracted from the output of the first adder/subtracter to accomplish the necessary correction from binary to binary coded decimal. The second full adder/subtracter is modified so as to permit generation of the two''s complement of a BCD digit applied at its input.

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