Switching architecture with packet encapsulation
    1.
    发明授权
    Switching architecture with packet encapsulation 有权
    具有封包封装的交换架构

    公开(公告)号:US09544080B2

    公开(公告)日:2017-01-10

    申请号:US14310743

    申请日:2014-06-20

    申请人: GENBAND US LLC

    摘要: The invention includes, among other things, a system for passing TDM traffic through a packet switch. In one embodiment, the system includes a packet switch that has a plurality of data ports and is capable of routing FSDU packets between the plurality of data ports. A TDM encapsulation circuit process a TDM data flow that is incoming to the switch. A circuit demultiplexer processes the incoming data flow to buffer data associated with different TDM circuits into different buffer locations. A timer monitors the amount of time available to fill the FSDU, and when the time period reaches the frame boundary, an FSDU generator generates an FSDU that is filled with data associated with the TDM circuits. Header information is added for allowing the packet switch to route the generated FSDU to a port associated with the respective TDM circuit.

    摘要翻译: 本发明尤其包括用于通过分组交换机传递TDM业务的系统。 在一个实施例中,系统包括具有多个数据端口并且能够在多个数据端口之间路由FSDU分组的分组交换机。 TDM封装电路处理进入交换机的TDM数据流。 电路解复用器处理进入的数据流,将与不同TDM电路相关联的数据缓冲到不同的缓冲器位置。 定时器监视可用于填充FSDU的时间量,并且当该时间段到达帧边界时,FSDU生成器生成填充有与TDM电路相关联的数据的FSDU。 添加标题信息以允许分组交换路由生成的FSDU到与相应TDM电路相关联的端口。

    SWITCHING ARCHITECTURE WITH PACKET ENCAPSULATION
    2.
    发明申请
    SWITCHING ARCHITECTURE WITH PACKET ENCAPSULATION 有权
    切换架构与分组封装

    公开(公告)号:US20140301398A1

    公开(公告)日:2014-10-09

    申请号:US14310743

    申请日:2014-06-20

    申请人: GENBAND US LLC

    IPC分类号: H04J3/16

    摘要: The invention includes, among other things, a system for passing TDM traffic through a packet switch. In one embodiment, the system includes a packet switch that has a plurality of data ports and is capable of routing FSDU packets between the plurality of data ports. A TDM encapsulation circuit process a TDM data flow that is incoming to the switch. A circuit demultiplexer processes the incoming data flow to buffer data associated with different TDM circuits into different buffer locations. A timer monitors the amount of time available to fill the FSDU, and when the time period reaches the frame boundary, an FSDU generator generates an FSDU that is filled with data associated with the TDM circuits. Header information is added for allowing the packet switch to route the generated FSDU to a port associated with the respective TDM circuit.

    摘要翻译: 本发明尤其包括用于通过分组交换机传递TDM业务的系统。 在一个实施例中,系统包括具有多个数据端口并且能够在多个数据端口之间路由FSDU分组的分组交换机。 TDM封装电路处理进入交换机的TDM数据流。 电路解复用器处理进入的数据流,将与不同TDM电路相关联的数据缓冲到不同的缓冲器位置。 定时器监视可用于填充FSDU的时间量,并且当该时间段到达帧边界时,FSDU生成器生成填充有与TDM电路相关联的数据的FSDU。 添加标题信息以允许分组交换路由生成的FSDU到与相应TDM电路相关联的端口。