公开(公告)号：US20190089350A1

公开(公告)日：2019-03-21

申请号：US16118518

申请日：2018-08-31

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Bo QU ,  Ying ZHANG ,  Marius Michael MECHLINSKI ,  Saijun MAO ,  Jingkui SHI ,  He XU ,  Zhihui YUAN ,  Jie SHEN ,  Stefan SCHROEDER

IPC: H03K17/30 ,  H02M1/088

Abstract: The present disclosure relates to a method for controlling voltage balance of a serialized power switching device, comprising generating a reference voltage based on actual individual voltage of each switch of the serialized power switching device or setting a reference voltage based on supplied voltage to the serialized power switching device; determining an individual blocking voltage mismatch of at least one switch when existing a difference between the reference voltage and the actual individual voltage of at least one switch, wherein the individual voltage mismatch is based on the difference between the reference voltage and the actual individual voltage; calculating an individual delay mismatch for the at least one switch; and compensating the individual delay mismatch for the at least one switch. The present disclosure also relates to a system for controlling voltage balance of a serialized power switching device. The present disclosure also relates to a power switching device.

公开(公告)号：US20180337109A1

公开(公告)日：2018-11-22

申请号：US15981975

申请日：2018-05-17

Applicant: General Electric Company

Inventor： Saijun MAO ,  Bo QU ,  Jingkui SHI ,  He XU ,  Jie SHEN ,  Lin LAN ,  Rui LI ,  Zhihui YUAN ,  Alistair Martin WADDELL ,  Stefan SCHROEDER ,  Marius Michael MECHLINSKI ,  Mark Aaron CHAN

IPC: H01L23/473 ,  H01L23/367 ,  H01L25/07

CPC classification number: H01L23/473 ,  H01L25/072

Abstract: The present disclosure relates to an integrated power semiconductor packaging apparatus and a power converter containing the integrated power semiconductor packaging apparatus. The integrated power semiconductor packaging apparatus comprises a plurality of power semiconductor devices and an electrically insulative substrate formed integrally. The electrically insulative substrate comprises a flat surface, at least one separation wall protruding from the flat surface and a flow channel inside the electrically insulative substrate. The at least one separation wall is configured to separate the flat surface into a plurality of flat areas, and each of the plurality of flat areas is configured to receive one of the plurality of power semiconductor devices. The flow channel is configured for allowing a coolant flowing through to remove heat from the plurality of power semiconductor devices.