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公开(公告)号：US20070234009A1
公开(公告)日：2007-10-04
申请号：US11758892
申请日：2007-06-06
IPC分类号： G06F9/40
CPC分类号： G06F9/3851
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. Instructions for switching and branching based on executing contexts are also disclosed.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程或上下文的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。 还公开了基于执行上下文的切换和分支的指令。
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公开(公告)号：US20090119671A1
公开(公告)日：2009-05-07
申请号：US12249786
申请日：2008-10-10
申请人： GILBERT WOLRICH , Mark B. Rosenbluth , Debra Bernstein , Matthew Adiletta , Hugh M. Wilkinson, III
发明人： GILBERT WOLRICH , Mark B. Rosenbluth , Debra Bernstein , Matthew Adiletta , Hugh M. Wilkinson, III
CPC分类号： G06F9/4843 , G06F9/30101 , G06F9/3012 , G06F9/30123 , G06F9/3851
摘要： A system and method for employing registers for data transfer in multiple hardware contexts and programming engines to facilitate high performance data processing. The system and method includes a processor that includes programming engines with registers for transferring data from one of the registers residing in an executing programming engine to a subsequent one of the registers residing in an adjacent programming engine.
摘要翻译： 一种用于在多个硬件上下文和编程引擎中采用用于数据传输的寄存器以便于高性能数据处理的系统和方法。 该系统和方法包括处理器，其包括具有寄存器的编程引擎，用于将驻留在执行编程引擎中的寄存器中的一个寄存器中的数据传送到驻留在相邻编程引擎中的后续寄存器中的寄存器。
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3.发明申请INSTRUCTION-SET ARCHITECTURE FOR PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) COMPUTATIONS 审中-公开可编程循环冗余检查（CRC）计算的指导体系结构公开(公告)号：US20140229807A1
公开(公告)日：2014-08-14
申请号：US14254233
申请日：2014-04-16
申请人： VINODH GOPAL , SHAY GUERON , GILBERT WOLRICH , WAJDI FEGHALI , KIRK YAP , BRADLEY BURRES
发明人： VINODH GOPAL , SHAY GUERON , GILBERT WOLRICH , WAJDI FEGHALI , KIRK YAP , BRADLEY BURRES
CPC分类号： G06F9/30145 , G06F9/30018 , G06F11/1004 , H03M13/09 , H03M13/091
摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
摘要翻译： 提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。 灵活的CRC指令使用可编程的n位多项式来执行CRC操作。 通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。
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4.发明申请INSTRUCTION-SET ARCHITECTURE FOR PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) COMPUTATIONS 有权可编程循环冗余检查（CRC）计算的指导体系结构公开(公告)号：US20130191699A1
公开(公告)日：2013-07-25
申请号：US13793358
申请日：2013-03-11
申请人： VINODH GOPAL , SHAY GUERON , GILBERT WOLRICH , WAJDI FEGHALI , KIRK YAP , BRADLEY BURRES
发明人： VINODH GOPAL , SHAY GUERON , GILBERT WOLRICH , WAJDI FEGHALI , KIRK YAP , BRADLEY BURRES
IPC分类号： H03M13/09
CPC分类号： G06F9/30145 , G06F9/30018 , G06F11/1004 , H03M13/09 , H03M13/091
摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
摘要翻译： 提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。 灵活的CRC指令使用可编程的n位多项式来执行CRC操作。 通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。
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