公开(公告)号：US09620589B2

公开(公告)日：2017-04-11

申请号：US14246983

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Nicolas Sassiat ,  Ran Yan ,  Kun-Hsien Lin ,  Jan Hoentschel

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/0673 ,  H01L21/30608 ,  H01L21/3083 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.

公开(公告)号：US20150287782A1

公开(公告)日：2015-10-08

申请号：US14246983

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Nicolas Sassiat ,  Ran Yan ,  Kun-Hsien Lin ,  Jan Hoentschel

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/30608 ,  H01L21/3083 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种方法包括提供半导体衬底，在半导体衬底上限定对应于纳米线的相对顶点的长度，去除半导体衬底的一部分以提供第一鳍结构和第二鳍结构，蚀刻第一腔 在所述第一侧附近沉积保护层，去除所述保护层的一部分以暴露所述半导体衬底的一部分，以及蚀刻所述第一和第二腔连通的所述暴露的半导体衬底处的第二腔。 第一鳍片结构和第二鳍片结构相邻，其中第一鳍片结构的长度对应于相对的顶点，并且具有第一侧面和第二侧面。

公开(公告)号：US09460955B2

公开(公告)日：2016-10-04

申请号：US14092232

申请日：2013-11-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Alban Zaka ,  Kun-Hsien Lin

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.

Abstract translation: 提供了具有靠近浅沟槽隔离的电气部件的集成电路以及用于制造这种集成电路的方法。 该方法包括形成沟槽是衬底，其中沟槽具有沟槽表面。 包括硅和锗的阻挡层形成在沟槽表面上。 然后用覆盖阻挡层的芯形成浅沟槽隔离，其中芯包括浅沟槽隔离绝缘体。

公开(公告)号：US20150145000A1

公开(公告)日：2015-05-28

申请号：US14092232

申请日：2013-11-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Alban Zaka ,  Kun-Hsien Lin

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.

Abstract translation: 提供了具有靠近浅沟槽隔离的电气部件的集成电路以及用于制造这种集成电路的方法。 该方法包括形成沟槽是衬底，其中沟槽具有沟槽表面。 包括硅和锗的阻挡层形成在沟槽表面上。 然后用覆盖阻挡层的芯形成浅沟槽隔离，其中芯包括浅沟槽隔离绝缘体。