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公开(公告)号：US20160149595A1
公开(公告)日：2016-05-26
申请号：US14548929
申请日：2014-11-20
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Yiftach Benjamini , Adrian S. Butter
CPC classification number: G06F11/10 , H03M13/03 , H03M13/333 , H04L1/00 , H04L1/004 , H04L1/008 , H04L27/2655
Abstract: Techniques for forward error correction synchronization are described herein. The techniques include receiving a bit stream over a transmission link and determining a starting location of a first code word within the bit stream. Determining the starting location of the first code word includes identifying an error correction block associated with a previously received second code word, and designating a bit subsequent to the error correction block as the starting location of the first code word.
Abstract translation: 本文描述了用于前向纠错同步的技术。 这些技术包括通过传输链路接收比特流并确定比特流内的第一码字的起始位置。 确定第一码字的起始位置包括识别与先前接收到的第二码字相关联的纠错块，以及将纠错块之后的位指定为第一码字的起始位置。
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公开(公告)号：US09465689B2
公开(公告)日：2016-10-11
申请号：US14548929
申请日：2014-11-20
Applicant: GLOBALFOUNDRIES Inc.
Inventor： Yiftach Benjamini , Adrian S. Butter
CPC classification number: G06F11/10 , H03M13/03 , H03M13/333 , H04L1/00 , H04L1/004 , H04L1/008 , H04L27/2655
Abstract: Techniques for forward error correction synchronization are described herein. The techniques include receiving a bit stream over a transmission link and determining a starting location of a first code word within the bit stream. Determining the starting location of the first code word includes identifying an error correction block associated with a previously received second code word, and designating a bit subsequent to the error correction block as the starting location of the first code word.
Abstract translation: 本文描述了用于前向纠错同步的技术。 这些技术包括通过传输链路接收比特流并确定比特流内的第一码字的起始位置。 确定第一码字的起始位置包括识别与先前接收到的第二码字相关联的纠错块，以及将纠错块之后的位指定为第一码字的起始位置。
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公开(公告)号：US09606604B1
公开(公告)日：2017-03-28
申请号：US14951544
申请日：2015-11-25
Applicant: GLOBALFOUNDRIES INC.
Inventor： Adrian S. Butter
CPC classification number: G06F1/3209 , Y02D70/122 , Y02D70/44
Abstract: In high-speed link structures a receiver outputs a signal detect indicator (SDI) with a first logic value when transmissions are detected and a second logic value when suspension of transmissions is detected. A controller detects transitions in the SDI and causes corresponding transitions in an energy detect indicator (EDI). A physical control sublayer (PCS) has different operating states that cause the receiver to operate in different power modes and transitions between the operating states based on the EDI. If the EDI has the second logic value, the PCS remains in a non-active state and the receiver operates in a low power idle (LPI) mode. When the EDI transitions to the first logic value, the PCS exits the non-active state and the receiver operates in a non-LPI mode. To ensure that the PCS properly enters and doesn't pre-maturely exit the non-active state, EDI transitions to the first logic value are delayed.
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