公开(公告)号：US09916896B1

公开(公告)日：2018-03-13

申请号：US15340579

申请日：2016-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Robert M. Houle ,  Michael T. Fragano ,  Akhilesh Patil ,  Van D. Butler

IPC: G11C7/00 ,  G11C15/04 ,  G11C29/12

CPC classification number: G11C15/04 ,  G11C7/12 ,  G11C29/021 ,  G11C29/025 ,  G11C29/026 ,  G11C29/12 ,  G11C2029/1204

Abstract: The present disclosure relates to a pre-charge circuit including a first inverter which receives an early pre-charge signal and outputs an inverted early pre-charge signal, a first gate which receives a late pre-charge signal and a match line output signal and outputs an AND output signal, and a second gate which receives the inverted early pre-charge signal and the AND output signal and outputs an effective pre-charge signal.

公开(公告)号：US10796750B2

公开(公告)日：2020-10-06

申请号：US16031439

申请日：2018-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Akhilesh Patil ,  Eric D. Hunt-Schroeder

IPC: G11C7/12 ,  G11C11/419 ,  G11C11/4074 ,  G11C11/4076

Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.

公开(公告)号：US20200020388A1

公开(公告)日：2020-01-16

申请号：US16031439

申请日：2018-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Akhilesh Patil ,  Eric D. Hunt-Schroeder

IPC: G11C11/419 ,  G11C7/12 ,  G11C11/4076 ,  G11C11/4074

Abstract: The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.