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    Sensing circuits for charge trap transistors
    1.
    发明授权
    Sensing circuits for charge trap transistors 有权

    公开(公告)号：US11101010B2

    公开(公告)日：2021-08-24

    申请号：US16568394

    申请日：2019-09-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric D. Hunt-Schroeder ,  Sebastian T. Ventrone ,  James A. Svarczkopf ,  Igor Arsovski

    IPC: G11C17/18 ,  G11C7/06 ,  G11C7/08 ,  G11C11/409

    Abstract: The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.

    Application specific integrated circuit (ASIC) test screens and selection of such screens
    7.
    发明授权
    Application specific integrated circuit (ASIC) test screens and selection of such screens 有权

    公开(公告)号：US09760673B2

    公开(公告)日：2017-09-12

    申请号：US15012331

    申请日：2016-02-01

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric D. Hunt-Schroeder ,  John R. Goss ,  Igor Arsovski ,  Paul J. Grzymkowski

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/64

    Abstract: Various embodiments include approaches for analyzing a customer design for an application specific integrated circuit (ASIC). In some cases, an approach includes: determining performance requirements of the customer design; querying a test screen database for the performance requirements of the customer design, the test screen database having failure thresholds and associated test screens for detecting the failure thresholds for a set of ASIC devices; generating a filter database including select failure thresholds and associated test screens for the performance requirements of the customer design; and selecting a set of test screens from the filter database based upon a yield cost criteria in forming the ASIC.

    DOUBLE BANDWIDTH ALGORITHMIC MEMORY ARRAY
    10.
    发明申请
    DOUBLE BANDWIDTH ALGORITHMIC MEMORY ARRAY 有权

    公开(公告)号：US20170315738A1

    公开(公告)日：2017-11-02

    申请号：US15140016

    申请日：2016-04-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Eric D. Hunt-Schroeder ,  Mark W. Kuemerle

    IPC: G06F3/06

    CPC classification number: G06F11/108

    Abstract: The present disclosure relates to memory structures and, more particularly, to double bandwidth algorithmic memory array structures and methods of use. The memory array includes: a plurality of memory banks each of which includes addressable storage units; a redundant array of independent disks (RAID) bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address; and a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to refresh the parity bits in the RAID bank.

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