公开(公告)号：US10248754B2

公开(公告)日：2019-04-02

申请号：US15602810

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Fadi Batarseh ,  Karthik Krishnamoorthy ,  Ahmed Omran

IPC: G06F17/50

Abstract: An identification of a first area of an IC design surrounding a failure component is received; and, in response, a smaller portion of the first area is selected. The smaller portion also surrounds the failure component, is smaller than the first area, and contains less circuit components than the first area. The smaller portion is matched to other areas of the IC design to identify potentially undesirable patterns of the IC design that are the same size as the first area. Additionally, the potentially undesirable patterns are grouped into pattern categories, the pattern categories are matched to known good pattern categories, and the known good patterns are removed from the potentially undesirable patterns to leave potential failure patterns. The potential failure patterns of the IC design are then output.

公开(公告)号：US20180341739A1

公开(公告)日：2018-11-29

申请号：US15602810

申请日：2017-05-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Fadi Batarseh ,  Karthik Krishnamoorthy ,  Ahmed Omran

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: An identification of a first area of an IC design surrounding a failure component is received; and, in response, a smaller portion of the first area is selected. The smaller portion also surrounds the failure component, is smaller than the first area, and contains less circuit components than the first area. The smaller portion is matched to other areas of the IC design to identify potentially undesirable patterns of the IC design that are the same size as the first area. Additionally, the potentially undesirable patterns are grouped into pattern categories, the pattern categories are matched to known good pattern categories, and the known good patterns are removed from the potentially undesirable patterns to leave potential failure patterns. The potential failure patterns of the IC design are then output.