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    Integrated circuit (IC) design analysis and feature extraction
    1.
    发明授权
    Integrated circuit (IC) design analysis and feature extraction 有权

    公开(公告)号：US09754071B1

    公开(公告)日：2017-09-05

    申请号：US15048066

    申请日：2016-02-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Haraprasad Nanjundappa ,  Basanth Jagannathan ,  Laura S. Chadwick ,  Dureseti Chidambarrao ,  Christopher V. Baiocco

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.

    INTEGRATED CIRCUIT (IC) DESIGN ANALYSIS AND FEATURE EXTRACTION
    2.
    发明申请
    INTEGRATED CIRCUIT (IC) DESIGN ANALYSIS AND FEATURE EXTRACTION 有权

    公开(公告)号：US20170242952A1

    公开(公告)日：2017-08-24

    申请号：US15048066

    申请日：2016-02-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Haraprasad Nanjundappa ,  Basanth Jagannathan ,  Laura S. Chadwick ,  Dureseti Chidambarrao ,  Christopher V. Baiocco

    IPC: G06F17/50

    CPC classification number: G06F17/5081

    Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.

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