公开(公告)号：US10109526B1

公开(公告)日：2018-10-23

申请号：US15609408

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Nicholas V. LiCausi ,  J. Jay McMahon ,  Ryan S. Smith ,  Errol Todd Ryan ,  Shao Beng Law

IPC: H01L21/768

Abstract: Structures for a skip via and methods of forming a skip via in an interconnect structure. A metallization level is formed that includes a dielectric layer with a top surface. An opening is formed that extends vertically from the top surface of the dielectric layer into the dielectric layer. A dielectric cap layer is deposited on a bottom surface of the opening. A fill layer is formed inside the opening and extends from the top surface of the dielectric layer to the dielectric cap layer on the bottom surface of the opening. A via opening is etched that extends vertically through the fill layer to the dielectric cap layer on the bottom surface of the opening.

公开(公告)号：US10485111B2

公开(公告)日：2019-11-19

申请号：US15647400

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng Law ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  James McMahon ,  Ryan S. Smith ,  Xunyuan Zhang

IPC: H05K3/46 ,  H05K3/40 ,  H05K1/11 ,  H01L21/768

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.

公开(公告)号：US20190027401A1

公开(公告)日：2019-01-24

申请号：US15653638

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： James McMahon ,  Ryan S. Smith ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  Xunyuan Zhang ,  Shao Beng Law

IPC: H01L21/768 ,  H01L23/522

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dielectric repair for via and skip via structures and methods of manufacture. The method includes: etching a via structure in a dielectric layer; repairing sidewalls of the via structure with a repair agent; and extending the via structure with an additional etching into a lower dielectric layer to form a skip via structure exposing a metallization layer.

公开(公告)号：US10199261B1

公开(公告)日：2019-02-05

申请号：US15653638

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： James McMahon ,  Ryan S. Smith ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  Xunyuan Zhang ,  Shao Beng Law

IPC: H01L21/768 ,  H01L23/522

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dielectric repair for via and skip via structures and methods of manufacture. The method includes: etching a via structure in a dielectric layer; repairing sidewalls of the via structure with a repair agent; and extending the via structure with an additional etching into a lower dielectric layer to form a skip via structure exposing a metallization layer.

公开(公告)号：US20190021176A1

公开(公告)日：2019-01-17

申请号：US15647400

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shao Beng Law ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  James McMahon ,  Ryan S. Smith ,  Xunyuan Zhang

IPC: H05K3/46 ,  H05K3/40 ,  H05K1/11

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a first metallization layer with a first capping layer over the first metallization layer; forming a second metallization layer with a second capping layer over the second metallization layer; forming a partial skip via structure to the first metallization layer by removing a portion of the first capping layer and the second capping and depositing conductive material in an opening formed in the second metallization layer; forming a third capping layer over the filled partial skip via and the second capping layer; and forming a remaining portion of a skip via structure in alignment with the partial skip via structure by opening the third capping layer to expose the conductive material of the partial skip via.