公开(公告)号：US10707119B1

公开(公告)日：2020-07-07

申请号：US16246847

申请日：2019-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Jeremy A. Wahl ,  Vimal K. Kamineni

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level includes a metallization level having a first interconnect with a first top surface, a second interconnect with a second top surface, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first top surface of the first interconnect and a second section arranged on the second top surface of the second interconnect. The first section of the first dielectric layer is separated from the second section of the first dielectric layer by the entrance of the cavity. A second dielectric layer is arranged to surround the cavity and to close the entrance to the cavity in order to encapsulate an airgap inside the cavity.

公开(公告)号：US20200066585A1

公开(公告)日：2020-02-27

申请号：US16106246

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Christian Witt ,  Mark V. Raymond ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/532

Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.

公开(公告)号：US10109526B1

公开(公告)日：2018-10-23

申请号：US15609408

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Nicholas V. LiCausi ,  J. Jay McMahon ,  Ryan S. Smith ,  Errol Todd Ryan ,  Shao Beng Law

IPC: H01L21/768

Abstract: Structures for a skip via and methods of forming a skip via in an interconnect structure. A metallization level is formed that includes a dielectric layer with a top surface. An opening is formed that extends vertically from the top surface of the dielectric layer into the dielectric layer. A dielectric cap layer is deposited on a bottom surface of the opening. A fill layer is formed inside the opening and extends from the top surface of the dielectric layer to the dielectric cap layer on the bottom surface of the opening. A via opening is etched that extends vertically through the fill layer to the dielectric cap layer on the bottom surface of the opening.

公开(公告)号：US09570394B1

公开(公告)日：2017-02-14

申请号：US15140808

申请日：2016-04-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/4763 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/32051 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/7684 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

Abstract: Embodiments of the present disclosure may provide methods of forming an IC structure with a pair of metal fins. An IC structure with a pair of metal fins can include two unitary metal fins positioned on a substrate and each including an elongated wire positioned on the substrate and a via positioned directly on a portion of the elongated wire, the elongated wire and the via of each unitary metal fin defining an inverted T-shape, wherein each unitary metal fin includes the elongated wire with a pair of opposing sidewalls substantially coplanar with a pair of opposing sidewalls of the via, and wherein the each unitary metal fin includes a single crystallographic orientation. An insulating layer can be positioned directly laterally between the two unitary metal fins.

Abstract translation: 本公开的实施例可以提供用一对金属翅片形成IC结构的方法。 具有一对金属翅片的IC结构可以包括位于基底上的两个单一金属翅片，每个包括位于基底上的细长线和直接位于细长线的一部分上的通孔，细长线和每个 一体式金属翅片限定了倒T形，其中每个单一金属翅片包括具有一对相对的侧壁的细长线，所述相对的侧壁与通孔的一对相对的侧壁基本共面，并且其中每个单一金属翅片包括单晶取向。 绝缘层可以直接横向放置在两个单一金属翅片之间。

公开(公告)号：US20150129934A1

公开(公告)日：2015-05-14

申请号：US14079159

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L21/8234

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Abstract translation: 所公开的一种方法包括通过栅极腔执行选择性蚀刻工艺，以相对于第二半导体材料和衬底的第二层选择性地去除第一半导体材料的一部分，从而限定第二半导体材料与第二半导体材料之间的空间 衬底，用绝缘材料填充基本上所有的空间，从而限定位于至少将成为FinFET器件的沟道区的至少自对准沟道隔离区。

公开(公告)号：US08846511B2

公开(公告)日：2014-09-30

申请号：US13764839

申请日：2013-02-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Jeremy A. Wahl

IPC: H01L21/00 ,  H01L29/66

CPC classification number: H01L29/66477 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

Abstract: One illustrative method disclosed herein includes forming an initial nanowire structure having an initial cross-sectional size, performing a doping diffusion process to form an N-type doped region in the initial nanowire structure and performing an etching process to remove at least a portion of the doped region and thereby define a final nanowire structure having a final cross-sectional size, wherein the final cross-sectional size is smaller than the initial cross-sectional size.

Abstract translation: 本文公开的一种说明性方法包括形成具有初始横截面尺寸的初始纳米线结构，执行掺杂扩散工艺以在初始纳米线结构中形成N型掺杂区，并执行蚀刻工艺以去除至少一部分 从而限定具有最终横截面尺寸的最终纳米线结构，其中最终横截面尺寸小于初始横截面尺寸。

公开(公告)号：US10677855B2

公开(公告)日：2020-06-09

申请号：US15699094

申请日：2017-09-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LiCausi

IPC: G01R31/50 ,  H01L23/528 ,  H01L21/66 ,  H01L21/311 ,  H01L21/768 ,  G01R31/26 ,  H01L23/544 ,  G01R31/28 ,  H01L21/3065 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/522

Abstract: Structures for measuring RIE lag depth of a semiconductor device, including: a first metal layer; a dielectric cap layer on top of the first metal layer; an electrical ground element formed beneath one or more portions of the dielectric cap layer and within the first metal layer, the electrical ground element being electrically grounded; and a second metal layer on top of the dielectric cap layer, the second metal layer having an array of one or more sub-arrays of metal wires, each sub-array being connected to a respective bond pad and having metal wires of a given width; wherein a distance from a bottom surface of the array of metal wires to a top surface of the dielectric cap layer is indicative of RIE lag depth. The disclosure also relates to methods and systems for measuring RIE lag depth and identifying the existence of an electrical short of a semiconductor device.

公开(公告)号：US10283372B2

公开(公告)日：2019-05-07

申请号：US15705956

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Mark V. Raymond ,  Errol Todd Ryan ,  Nicholas V. LiCausi

IPC: H01L27/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532

Abstract: Methods of forming interconnects. An interconnect opening is formed in a dielectric layer. A first conductor layer composed of a first metal is formed in the interconnect opening. A second conductor layer is formed inside the interconnect opening by displacing the first metal of the first conductor layer and replacing the first metal with a second metal different from the first metal.

公开(公告)号：US20190079128A1

公开(公告)日：2019-03-14

申请号：US15699094

申请日：2017-09-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LiCausi

IPC: G01R31/02 ,  H01L21/66 ,  H01L23/528 ,  H01L23/522 ,  H01L21/311 ,  H01L21/768 ,  G01R31/26

Abstract: Structures for measuring RIE lag depth of a semiconductor device, including: a first metal layer; a dielectric cap layer on top of the first metal layer; an electrical ground element formed beneath one or more portions of the dielectric cap layer and within the first metal layer, the electrical ground element being electrically grounded; and a second metal layer on top of the dielectric cap layer, the second metal layer having an array of one or more sub-arrays of metal wires, each sub-array being connected to a respective bond pad and having metal wires of a given width; wherein a distance from a bottom surface of the array of metal wires to a top surface of the dielectric cap layer is indicative of RIE lag depth. The disclosure also relates to methods and systems for measuring RIE lag depth and identifying the existence of an electrical short of a semiconductor device.

公开(公告)号：US10199261B1

公开(公告)日：2019-02-05

申请号：US15653638

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： James McMahon ,  Ryan S. Smith ,  Nicholas V. LiCausi ,  Errol Todd Ryan ,  Xunyuan Zhang ,  Shao Beng Law

IPC: H01L21/768 ,  H01L23/522

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dielectric repair for via and skip via structures and methods of manufacture. The method includes: etching a via structure in a dielectric layer; repairing sidewalls of the via structure with a repair agent; and extending the via structure with an additional etching into a lower dielectric layer to form a skip via structure exposing a metallization layer.