公开(公告)号：US20190392110A1

公开(公告)日：2019-12-26

申请号：US16013403

申请日：2018-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gazi M. Huda ,  Samuel O. Nakagawa

IPC: G06F17/50 ,  H01L27/02 ,  H01L21/321

Abstract: The disclosure provides a method including: identifying a fill-dense region of an integrated circuit (IC) layout having a plurality of fill cells, and a target fill region of the IC layout adjacent to the fill-dense region and free of fill cells; modifying the IC layout by removing a fill cell from the fill-dense region and inserting a duplicate of the removed fill cell within the target fill region to at least partially fill the target fill region; and providing instructions to manufacture an IC using the modified IC layout. The method may reduce a feature density of the fill-dense region to less than an allowable feature density, while adding fill features to otherwise unfillable regions.

公开(公告)号：US10691865B2

公开(公告)日：2020-06-23

申请号：US16013403

申请日：2018-06-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Gazi M. Huda ,  Samuel O. Nakagawa

IPC: G06F17/50 ,  G06F30/398 ,  H01L21/321 ,  H01L27/02 ,  G03F7/20

Abstract: The disclosure provides a method including: identifying a fill-dense region of an integrated circuit (IC) layout having a plurality of fill cells, and a target fill region of the IC layout adjacent to the fill-dense region and free of fill cells; modifying the IC layout by removing a fill cell from the fill-dense region and inserting a duplicate of the removed fill cell within the target fill region to at least partially fill the target fill region; and providing instructions to manufacture an IC using the modified IC layout. The method may reduce a feature density of the fill-dense region to less than an allowable feature density, while adding fill features to otherwise unfillable regions.