公开(公告)号：US20150170735A1

公开(公告)日：2015-06-18

申请号：US14105939

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. PAUL ,  Randy W. MANN ,  Sangmoon J. KIM

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C8/16 ,  H01L27/0207 ,  H01L27/1104

Abstract: Dual port static random access memory (SRAM) bitcell structures with improve symmetry in access transistors physical placement are provided. The bitcell structures may include, for example, two pairs of parallel pull-down transistors. The bitcell structures may also include pass-gate transistors PGLA and PGRA forming a first port, and pass-gate transistors PGLB and PGRB forming a second port. The pass-gate transistors PGLA and PGLB may be adjacent one another and a first side of the bitcell structure, and pass-gate transistors PGRA and PGRB may be adjacent one another and a second side of the bitcell structure. Each of the pass-gate transistors PGLA and PGLB may be connected with one of the pull-down transistors of one of the pairs of parallel pull-down transistors. Similarly, each of the pass-gate transistors PGRA and PGRB may be connected with one of the pull-down transistors of the other pair of parallel pull-down transistors.

Abstract translation: 提供了具有提高存取晶体管物理放置对称性的双端口静态随机存取存储器（SRAM）位单元结构。 比特单元结构可以包括例如两对并行下拉晶体管。 比特单元结构还可以包括形成第一端口的通过栅极晶体管PGLA和PGRA，以及形成第二端口的通过栅极晶体管PGLB和PGRB。 通路栅极晶体管PGLA和PGLB可以彼此相邻，并且位单元结构的第一侧，以及栅极晶体管PGRA和PGRB可以彼此相邻，并且位单元结构的第二侧。 每个通栅晶体管PGLA和PGLB可以与一对并联下拉晶体管中的一个的下拉晶体管中的一个连接。 类似地，每个通栅晶体管PGRA和PGRB可以与另一对并联下拉晶体管的下拉晶体管中的一个连接。