公开(公告)号：US20180012647A1

公开(公告)日：2018-01-11

申请号：US15711714

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hema Ramamurthy ,  Sanjay Parihar ,  Jongsin Yun

IPC: G11C11/412 ,  G11C11/419 ,  H01L27/11 ,  H01L27/12

CPC classification number: G11C11/412 ,  G11C11/419 ,  H01L27/1104 ,  H01L27/1112 ,  H01L27/1203

Abstract: At least one method, apparatus and system disclosed involves a memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled to a second bit line signal and the word line signal; a first pull down (PD) NMOS transistor operatively coupled to the first PG NMOS transistor; a second PD NMOS transistor operatively coupled to the second PG NMOS transistor; a first pull up (PU) NMOS transistor operatively coupled to the first PD NMOS transistor; and a second PU NMOS transistor operatively coupled to the second PD NMOS transistor. Each of the back gates of the first and second PU NMOS transistors are coupled to a predetermined voltage signal for biasing the first and second PU NMOS transistors.

公开(公告)号：US09799393B1

公开(公告)日：2017-10-24

申请号：US15169342

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hema Ramamurthy ,  Sanjay Parihar ,  Jongsin Yun

IPC: G11C11/41 ,  G11C11/412 ,  H01L27/11 ,  G11C11/419 ,  H01L27/12

CPC classification number: G11C11/412 ,  G11C11/419 ,  H01L27/1104 ,  H01L27/1112 ,  H01L27/1203

Abstract: A memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled to a second bit line signal and the word line signal; a first pull down (PD) NMOS transistor operatively coupled to the first PG NMOS transistor; a second PD NMOS transistor operatively coupled to the second PG NMOS transistor; a first pull up (PU) NMOS transistor operatively coupled to the first PD NMOS transistor; and a second PU NMOS transistor operatively coupled to the second PD NMOS transistor. Each of the back gates of the first and second PU NMOS transistors are coupled to a predetermined voltage signal for biasing the first and second PU NMOS transistors.