公开(公告)号：US10347531B2

公开(公告)日：2019-07-09

申请号：US15438828

申请日：2017-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Xusheng Wu ,  Xinyuan Dou ,  Xiaobo Chen ,  Guoliang Zhu ,  Wenhe Lin ,  Jeffrey Chee

IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

Abstract: Disclosed are a method of forming an integrated circuit (IC) structure with robust metal plugs and the resulting IC structure. In the method, openings are formed in an interlayer dielectric layer to expose semiconductor device surfaces. The openings are lined with a two-layer liner, which includes conformal metal and barrier layers, and subsequently filled with a metal layer. However, instead of waiting until after the liner is formed to perform a silicidation anneal, as is conventionally done, the silicidation anneal is performed between deposition of the two liner layers. This is particularly useful because, as determined by the inventors, performing the silicidation anneal prior to depositing the conformal barrier layer prevents the formation of microcracks in the conformal barrier layer. Prevention of such microcracks, in turn, prevents any metal from the metal layer from protruding into the area between the two liner layers and/or completely through the liner.