公开(公告)号：US10469041B2

公开(公告)日：2019-11-05

申请号：US15886475

申请日：2018-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony Kendall Stamper ,  Vibhor Jain ,  Humberto Campanella Pineda ,  John Joseph Pekarik

IPC: H01L27/06 ,  H03F3/21 ,  H01L21/304 ,  H01L21/8238 ,  H01L27/02 ,  H01L21/762 ,  H01L21/02

Abstract: A method of forming a CMOS device and a GaN PA structure on a 100 Si substrate having a surface orientated in 111 direction and the resulting device are provided. Embodiments include forming a device with a protective layer over a portion of a Si substrate; forming a V-shaped groove in the Si substrate; forming a buffer layer, a GaN layer, an AlGaN layer and a passivation layer sequentially over the Si substrate; forming trenches through the passivation and the AlGaN layers; forming second trenches through the passivation layer; forming electrode structures over portions of the passivation layer and filling the first and second trenches; removing portions of the passivation layer, the AlGaN layer and the GaN layer outside of the V-shaped groove down to the buffer layer; forming a dielectric layer over the Si substrate; and forming vias through the dielectric layer down to electrode structures and the device.

公开(公告)号：US09275951B2

公开(公告)日：2016-03-01

申请号：US13945678

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Felix Patrick Anderson ,  Thomas Leddy McDevitt ,  Anthony Kendall Stamper

IPC: H01L21/00 ,  H01L23/528 ,  H01G4/232 ,  H01G4/30 ,  H01G4/33 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01G4/232 ,  H01G4/306 ,  H01G4/33 ,  H01L21/768 ,  H01L23/5223 ,  H01L28/86 ,  H01L28/90 ,  H01L2924/0002 ,  Y10T29/49204 ,  H01L2924/00

Abstract: A method for reducing areas of high field density in an integrated circuit is disclosed. In one embodiment, the method includes forming a first curvilinear wiring structure in a first interconnect layer of an integrated circuit. A second curvilinear wiring structure may be formed in a second interconnect layer of the integrated circuit, such that the first and second curvilinear wiring structures are substantially vertically aligned. The first curvilinear wiring structure may then be electrically connected to the second curvilinear wiring structure. A corresponding apparatus and design structure are also described.

Abstract translation: 公开了一种用于减小集成电路中的高场强的区域的方法。 在一个实施例中，该方法包括在集成电路的第一互连层中形成第一曲线布线结构。 可以在集成电路的第二互连层中形成第二曲线布线结构，使得第一和第二曲线布线结构基本上垂直对齐。 然后可以将第一曲线性布线结构电连接到第二曲线布线结构。 还描述了相应的装置和设计结构。