公开(公告)号：US20190109192A1

公开(公告)日：2019-04-11

申请号：US15728679

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Damien Angot ,  Alban Zaka ,  Tom Herrmann ,  Venkata Naga Ranjith Kuma Nelluri ,  Jan Hoentschel ,  Lars Mueller-Meskamp ,  Martin Gerhardt

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.

公开(公告)号：US10580863B2

公开(公告)日：2020-03-03

申请号：US15728679

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Damien Angot ,  Alban Zaka ,  Tom Herrmann ,  Venkata Naga Ranjith Kuma Nelluri ,  Jan Hoentschel ,  Lars Mueller-Meskamp ,  Martin Gerhardt

IPC: H01L27/088 ,  H01L21/336 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/10 ,  H01L21/84 ,  H01L29/66 ,  H01L21/225 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.