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    Thin body field effect transistor including a counter-doped channel area and a method of forming the same
    3.
    发明授权
    Thin body field effect transistor including a counter-doped channel area and a method of forming the same 有权

    公开(公告)号：US10283642B1

    公开(公告)日：2019-05-07

    申请号：US15957072

    申请日：2018-04-19

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  El Mehdi Bazizi ,  Luca Pirro

    IPC分类号： H01L29/786 ,  H01L29/08

    摘要： Manufacturing techniques and related semiconductor devices are disclosed in which the channel region of analog transistors and/or transistors operated at higher supply voltages may be formed on the basis of a very thin semiconductor layer in an SOI configuration by incorporating a counter-doped region into the channel region at the source side of the transistor. The counter-doped region may be inserted prior to forming the gate electrode structure. With this asymmetric dopant profile in the channel region, superior transistor performance may be obtained, thereby obtaining a performance gain for transistors formed on the basis of a thin semiconductor base material required for the formation of sophisticated fully depleted transistor elements.

    Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure
    4.
    发明授权
    Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure 有权
    包括形成非易失性存储单元的控制栅极和半导体结构的方法

    公开(公告)号：US09583640B1

    公开(公告)日：2017-02-28

    申请号：US14982028

    申请日：2015-12-29

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Ralf Richter ,  Sven Beyer ,  Carsten Grass ,  Tom Herrmann

    IPC分类号： H01L29/788 ,  H01L29/66 ,  H01L29/423 ,  H01L27/115

    CPC分类号： H01L29/7887 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/665 ,  H01L29/66825 ,  H01L29/7881

    摘要： A method comprises providing a semiconductor structure including a nonvolatile memory cell element comprising a floating gate, a select gate and an erase gate formed over a semiconductor material, the select gate and the erase gate being arranged at opposite sides of the floating gate, forming a control gate insulation material layer over the semiconductor structure, forming a control gate material layer over the control gate insulation material layer, performing a first patterning process that forms a control gate over the floating gate and comprises a first etch process that selectively removes a material of the control gate material layer relative to a material of the control gate insulation material layer, and performing a second patterning process that patterns the control gate insulation material layer, the patterned control gate insulation material layer covering portions of the semiconductor structure that are not covered by the control gate.

    摘要翻译： 一种方法包括提供包括非易失性存储单元元件的半导体结构，所述非易失性存储单元元件包括在半导体材料上形成的浮置栅极，选择栅极和擦除栅极，所述选择栅极和擦除栅极被布置在所述浮置栅极的相对侧， 控制栅极绝缘材料层，在所述控制栅极绝缘材料层上方形成控制栅极材料层，执行在所述浮动栅极上形成控制栅极的第一图案化工艺，并且包括第一蚀刻工艺，所述第一蚀刻工艺选择性地去除 所述控制栅极材料层相对于所述控制栅极绝缘材料层的材料，并且执行对所述控制栅极绝缘材料层进行图案化的第二图案化工艺，所述图案化的控制栅极绝缘材料层覆盖所述半导体结构的不被 控制门。

    THRESHOLD VOLTAGE ADJUSTMENT IN A FIN TRANSISTOR BY CORNER IMPLANTATION
    5.
    发明申请
    THRESHOLD VOLTAGE ADJUSTMENT IN A FIN TRANSISTOR BY CORNER IMPLANTATION 有权
    通过角膜植入在晶状体中进行阈值电压调整

    公开(公告)号：US20140027825A1

    公开(公告)日：2014-01-30

    申请号：US14039450

    申请日：2013-09-27

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

    IPC分类号： H01L29/78

    CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886

    摘要： When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

    摘要翻译： 当在共同的制造顺序中形成复杂的多栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可以有意地“降低”多个栅极晶体管的阈值电压特性，从而获得 多个栅极晶体管和平面晶体管的阈值电压特性。 在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

    SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL AND METHOD FOR THE FORMATION THEREOF
    7.
    发明申请
    SEMICONDUCTOR STRUCTURE INCLUDING A NONVOLATILE MEMORY CELL AND METHOD FOR THE FORMATION THEREOF 有权
    包含非易失性存储单元的半导体结构及其形成方法

    公开(公告)号：US20170047336A1

    公开(公告)日：2017-02-16

    申请号：US14918048

    申请日：2015-10-20

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Alban Zaka ,  Sven Beyer ,  Tom Herrmann ,  El Mehdi Bazizi

    IPC分类号： H01L27/115 ,  H01L21/28

    CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

    摘要： A semiconductor structure includes a nonvolatile memory cell including a source region, a channel region and a drain region that are provided in a semiconductor material. The channel region includes a first portion adjacent the source region and a second portion between the first portion of the channel region and the drain region. An electrically insulating floating gate is provided over the first portion of the channel region. The nonvolatile memory cell further includes a select gate and a control gate. The first portion of the select gate is provided over the second portion of the channel region. The second portion of the select gate is provided over a portion of the floating gate that is adjacent to the first portion of the select gate. The control gate is provided over the floating gate and adjacent to the second portion of the select gate.

    摘要翻译： 半导体结构包括设置在半导体材料中的包括源极区，沟道区和漏极区的非易失性存储单元。 沟道区域包括邻近源极区域的第一部分和沟道区域的第一部分与漏极区域之间的第二部分。 在沟道区域的第一部分之上提供电绝缘的浮动栅极。 非易失性存储单元还包括选择栅极和控制栅极。 选择栅极的第一部分设置在沟道区域的第二部分上。 选择栅极的第二部分设置在与选择栅极的第一部分相邻的浮置栅极的一部分上。 控制栅极设置在浮动栅极上并且邻近选择栅极的第二部分。

    Threshold voltage adjustment in a fin transistor by corner implantation
    8.
    发明授权
    Threshold voltage adjustment in a fin transistor by corner implantation 有权
    通过角落植入对鳍式晶体管进行阈值电压调节

    公开(公告)号：US08916928B2

    公开(公告)日：2014-12-23

    申请号：US14039450

    申请日：2013-09-27

    申请人： GLOBALFOUNDRIES Inc.

    发明人： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

    IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/088

    CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886

    摘要： When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

    摘要翻译： 当在共同的制造顺序中形成复杂的多栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可以有意地“降低”多个栅极晶体管的阈值电压特性，从而获得 多个栅极晶体管和平面晶体管的阈值电压特性。 在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A VERTICAL NANOWIRE
    9.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A VERTICAL NANOWIRE 有权
    形成包括垂直纳米线的半导体结构的方法

    公开(公告)号：US20140206157A1

    公开(公告)日：2014-07-24

    申请号：US13747907

    申请日：2013-01-23

    申请人： GLOBALFOUNDRIES INC.

    发明人： Tim Baldauf ,  Stefan Flachowsky ,  Tom Herrmann ,  Ralf Illgen

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66666 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/775

    摘要： A method comprises providing a semiconductor structure comprising a substrate and a nanowire above the substrate. The nanowire comprises a first semiconductor material and extends in a vertical direction of the substrate. A material layer is formed above the substrate. The material layer annularly encloses the nanowire. A first part of the nanowire is selectively removed relative to the material layer. A second part of the nanowire is not removed. A distal end of the second part of the nanowire distal from the substrate is closer to the substrate than a surface of the material layer so that the semiconductor structure has a recess at the location of the nanowire. The distal end of the nanowire is exposed at the bottom of the recess. The recess is filled with a second semiconductor material. The second semiconductor material is differently doped than the first semiconductor material.

    摘要翻译： 一种方法包括提供包括衬底和衬底上方的纳米线的半导体结构。 纳米线包括第一半导体材料并沿着衬底的垂直方向延伸。 在衬底上形成材料层。 材料层环绕着纳米线。 相对于材料层选择性地去除纳米线的第一部分。 纳米线的第二部分不会被删除。 远离衬底的纳米线的第二部分的远端比材料层的表面更靠近衬底，使得半导体结构在纳米线的位置具有凹陷。 纳米线的远端暴露在凹槽的底部。 凹部填充有第二半导体材料。 第二半导体材料与第一半导体材料不同地掺杂。