Methods for forming FinFETs with reduced series resistance
    1.
    发明授权
    Methods for forming FinFETs with reduced series resistance 有权
    用于形成具有降低的串联电阻的FinFET的方法

    公开(公告)号:US09087720B1

    公开(公告)日:2015-07-21

    申请号:US14450535

    申请日:2014-08-04

    CPC classification number: H01L21/26513 H01L29/66795 H01L29/785

    Abstract: A method for forming FinFETs with reduced series resistance includes providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate, a gate disposed over a first portion of the fin, and a first sidewall spacer disposed over the fin and adjacent to the gate, increasing epitaxially the thickness of a second portion of the fin disposed outside the gate and the first sidewall spacer, and forming a second sidewall spacer disposed over the second portion of the fin and adjacent to the first sidewall spacer. A thickness of the second portion of the fin disposed under the second spacer is equal to or greater than a thickness of the first portion of the fin disposed under the gate.

    Abstract translation: 用于形成具有降低的串联电阻的FinFET的方法包括提供包括半导体衬底的中间半导体结构,设置在半导体衬底上的鳍,设置在鳍的第一部分上的栅极和设置在鳍上并邻近 到外部延伸设置在栅极和第一侧壁间隔物外部的翅片的第二部分的厚度,以及形成设置在翅片的第二部分上并邻近第一侧壁间隔物的第二侧壁间隔物。 设置在第二间隔件下方的翅片的第二部分的厚度等于或大于设置在浇口下方的翅片的第一部分的厚度。

Patent Agency Ranking