公开(公告)号：US10121846B1

公开(公告)日：2018-11-06

申请号：US15620923

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  El Mehdi Bazizi ,  John Morgan

IPC: H01L49/02 ,  H01L27/06

Abstract: The present disclosure provides resistor structures in sophisticated integrated circuits on the basis of an SOI architecture, wherein a very thin semiconductor layer, typically used for forming fully depleted SOI transistors, may be used as a resistor body. In this manner, significantly higher sheet resistance values may be achieved, thereby providing the potential for implementing high ohmic resistors into sophisticated integrated circuits.

公开(公告)号：US09583616B2

公开(公告)日：2017-02-28

申请号：US14643326

申请日：2015-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John Morgan

IPC: H01L27/12 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L29/7831 ,  H01L21/265 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1218 ,  H01L29/0649 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78654

Abstract: A semiconductor structure includes a semiconductor substrate, a plurality of transistors and an electrically insulating layer provided between the substrate and the plurality of transistors, and a trench isolation structure including a portion between a first and a second island of the semiconductor structure and extending into the substrate to a first depth. The substrate includes a bottom region having a first type of doping and extending at least to a second depth greater than the first depth, and a deep well region having a second type of doping and extending to a third depth greater than the first depth and smaller than the second depth. Each of the first and second islands includes a first backgate region having the first type of doping and being continuous with the bottom region and a second backgate region having the second type of doping and being continuous with the deep well region.

Abstract translation: 半导体结构包括半导体衬底，多个晶体管和设置在衬底和多个晶体管之间的电绝缘层，以及沟槽隔离结构，其包括半导体结构的第一和第二岛之间延伸到 衬底到第一深度。 衬底包括具有第一类型的掺杂并且延伸至少大于第一深度的第二深度的底部区域，以及具有第二类型掺杂并延伸到大于第一深度的第三深度的深阱区域，并且更小 比第二个深度。 第一岛和第二岛中的每一个包括具有第一类型掺杂并且与底部区域连续的第一背栅区区域和具有第二类型掺杂并与深阱区域连续的第二背栅区域。

公开(公告)号：US20160268424A1

公开(公告)日：2016-09-15

申请号：US14643326

申请日：2015-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John Morgan

IPC: H01L29/78 ,  H01L21/84 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/7831 ,  H01L21/265 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1218 ,  H01L29/0649 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78654

Abstract: A semiconductor structure includes a semiconductor substrate, a plurality of transistors and an electrically insulating layer provided between the substrate and the plurality of transistors, and a trench isolation structure including a portion between a first and a second island of the semiconductor structure and extending into the substrate to a first depth. The substrate includes a bottom region having a first type of doping and extending at least to a second depth greater than the first depth, and a deep well region having a second type of doping and extending to a third depth greater than the first depth and smaller than the second depth. Each of the first and second islands includes a first backgate region having the first type of doping and being continuous with the bottom region and a second backgate region having the second type of doping and being continuous with the deep well region.

Abstract translation: 半导体结构包括半导体衬底，多个晶体管和设置在衬底和多个晶体管之间的电绝缘层，以及沟槽隔离结构，其包括半导体结构的第一和第二岛之间延伸到 衬底到第一深度。 衬底包括具有第一类型的掺杂并且延伸至少大于第一深度的第二深度的底部区域，以及具有第二类型掺杂并延伸到大于第一深度的第三深度的深阱区域，并且更小 比第二个深度。 第一岛和第二岛中的每一个包括具有第一类型掺杂并且与底部区域连续的第一背栅区区域和具有第二类型掺杂并与深阱区域连续的第二背栅区域。