公开(公告)号：US20180286773A1

公开(公告)日：2018-10-04

申请号：US15996960

申请日：2018-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Maik Liebau ,  Matthias Lehr

IPC: H01L23/26 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528 ,  H01L23/522 ,  H01L21/66

Abstract: A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length. The one or more second portions have a second target dimension less than the first target dimension.

公开(公告)号：US20180158745A1

公开(公告)日：2018-06-07

申请号：US15367888

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Maik Liebau ,  Matthias Lehr

IPC: H01L23/26 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L23/26 ,  H01L21/56 ,  H01L21/76898 ,  H01L22/12 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L2224/4903 ,  H01L2224/94

Abstract: The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a “long” via line feature, superior sensitivity for variations of depth of focus may be achieved.

公开(公告)号：US20140273396A1

公开(公告)日：2014-09-18

申请号：US13827786

申请日：2013-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Maik Liebau ,  Ronny Pfuetzner

IPC: H01L49/02

CPC classification number: H01L28/40

Abstract: A method comprises forming a first layer of an electrically insulating material over a semiconductor structure. A recess is formed in the first layer of electrically insulating material. A capacitor layer stack is deposited over the first layer of electrically insulating material. The capacitor layer stack includes one or more bottom electrode layers, a dielectric layer and a top electrode layer, wherein a first portion of the capacitor layer stack is arranged in the recess and a second portion of the capacitor layer stack is arranged over a portion of the first layer of electrically insulating material adjacent the recess. A chemical mechanical polishing process is performed. The chemical mechanical polishing process removes the second portion of the capacitor layer stack, wherein the first portion of the capacitor layer stack is not removed.

Abstract translation: 一种方法包括在半导体结构上形成电绝缘材料的第一层。 在第一层电绝缘材料中形成凹部。 在电绝缘材料的第一层上沉积电容器层堆叠。 电容器层堆叠包括一个或多个底部电极层，电介质层和顶部电极层，其中电容器层堆叠的第一部分布置在凹部中，并且电容器层堆叠的第二部分布置在 邻近凹槽的第一层电绝缘材料。 进行化学机械抛光工艺。 化学机械抛光工艺去除电容器层堆叠的第二部分，其中电容器层堆叠的第一部分不被去除。

公开(公告)号：US10607947B2

公开(公告)日：2020-03-31

申请号：US15996960

申请日：2018-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Maik Liebau ,  Matthias Lehr

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L23/58

Abstract: A semiconductor device includes a metallization system positioned above a substrate and a die seal positioned at least in the metallization system and delimiting a die region. The die seal includes a via line feature having an axial length and including one or more first portions having a first target dimension and one or more second portions along the axial length. The one or more second portions have a second target dimension less than the first target dimension.

公开(公告)号：US10014234B2

公开(公告)日：2018-07-03

申请号：US15367888

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dirk Breuer ,  Maik Liebau ,  Matthias Lehr

IPC: H01L23/00 ,  H01L23/26 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L21/56 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L22/12 ,  H01L22/30 ,  H01L23/3107 ,  H01L23/585 ,  H01L2224/4903 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a “long” via line feature, superior sensitivity for variations of depth of focus may be achieved.

公开(公告)号：US08969170B2

公开(公告)日：2015-03-03

申请号：US13827786

申请日：2013-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Maik Liebau ,  Ronny Pfuetzner

IPC: H01L21/20 ,  H01L49/02

CPC classification number: H01L28/40

Abstract: A method comprises forming a first layer of an electrically insulating material over a semiconductor structure. A recess is formed in the first layer of electrically insulating material. A capacitor layer stack is deposited over the first layer of electrically insulating material. The capacitor layer stack includes one or more bottom electrode layers, a dielectric layer and a top electrode layer, wherein a first portion of the capacitor layer stack is arranged in the recess and a second portion of the capacitor layer stack is arranged over a portion of the first layer of electrically insulating material adjacent the recess. A chemical mechanical polishing process is performed. The chemical mechanical polishing process removes the second portion of the capacitor layer stack, wherein the first portion of the capacitor layer stack is not removed.

Abstract translation: 一种方法包括在半导体结构上形成电绝缘材料的第一层。 在第一层电绝缘材料中形成凹部。 在电绝缘材料的第一层上沉积电容器层堆叠。 电容器层堆叠包括一个或多个底部电极层，电介质层和顶部电极层，其中电容器层堆叠的第一部分布置在凹部中，并且电容器层堆叠的第二部分布置在 邻近凹槽的第一层电绝缘材料。 进行化学机械抛光工艺。 化学机械抛光工艺去除电容器层堆叠的第二部分，其中电容器层堆叠的第一部分不被去除。