公开(公告)号：US09666524B2

公开(公告)日：2017-05-30

申请号：US15098513

申请日：2016-04-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Moosung Chae ,  Larry Zhao

IPC: H01L23/535 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a barrier on both the sidewalls and bottom of a via and the resulting device are provided. Embodiments include forming a metal line in a substrate; forming a Si-based insulating layer over the metal line and the substrate; forming a via in the Si-based insulating layer down to the metal line; forming a dual-layer Mn/MnN on sidewalls and a bottom surface of the via; and filling the via with metal.

公开(公告)号：US09362228B2

公开(公告)日：2016-06-07

申请号：US14059498

申请日：2013-10-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Moosung Chae ,  Larry Zhao

IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a barrier on both the sidewalls and bottom of a via and the resulting device are provided. Embodiments include forming a metal line in a substrate; forming a Si-based insulating layer over the metal line and the substrate; forming a via in the Si-based insulating layer down to the metal line; forming a dual-layer Mn/MnN on sidewalls and a bottom surface of the via; and filling the via with metal.

Abstract translation: 提供了在通孔的侧壁和底部上形成阻挡层的方法以及所得到的器件。 实施例包括在基板中形成金属线; 在金属线和基板上形成Si基绝缘层; 在所述Si基绝缘层中形成通孔至所述金属线; 在通孔的侧壁和底表面上形成双层Mn / MnN; 并用金属填充通孔。

公开(公告)号：US20150108647A1

公开(公告)日：2015-04-23

申请号：US14061319

申请日：2013-10-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Moosung Chae ,  Larry Zhao

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76858 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed.

Abstract translation: 一种用于制造集成电路的方法包括提供覆盖半导体衬底的导电材料和覆盖导电材料的电介质材料，其中开口暴露导电材料的表面和电介质材料的侧壁，并选择性地沉积第一层 导电材料的表面上的阻挡材料，其中电介质材料的侧壁保持暴露，第一阻挡材料使得如果在退火过程中退火，则第一阻挡材料将扩散到导电材料中。 该方法还包括修改暴露表面上的第一阻挡材料以形成第二阻挡材料，第二阻挡材料使得在退火过程期间，第二阻挡材料不会扩散到导电材料中并沉积第二阻挡层 沿着开口的侧壁的第一阻挡材料。 此外，该方法包括退火半导体衬底。 还公开了根据前述方法制造的集成电路。

公开(公告)号：US09159610B2

公开(公告)日：2015-10-13

申请号：US14061319

申请日：2013-10-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Moosung Chae ,  Larry Zhao

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76858 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed.

Abstract translation: 一种用于制造集成电路的方法包括提供覆盖半导体衬底的导电材料和覆盖导电材料的电介质材料，其中开口暴露导电材料的表面和电介质材料的侧壁，并选择性地沉积第一层 导电材料的表面上的阻挡材料，其中电介质材料的侧壁保持暴露，第一阻挡材料使得如果在退火过程中退火，则第一阻挡材料将扩散到导电材料中。 该方法还包括修改暴露表面上的第一阻挡材料以形成第二阻挡材料，第二阻挡材料使得在退火过程期间，第二阻挡材料不会扩散到导电材料中并沉积第二阻挡层 沿着开口的侧壁的第一阻挡材料。 此外，该方法包括退火半导体衬底。 还公开了根据前述方法制造的集成电路。