公开(公告)号：US09159610B2

公开(公告)日：2015-10-13

申请号：US14061319

申请日：2013-10-23

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Moosung Chae ,  Larry Zhao

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76858 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating an integrated circuit includes providing a conductive material overlying a semiconductor substrate and a dielectric material overlying the conductive material, wherein an opening exposes a surface of the conductive material and sidewalls of the dielectric material and selectively depositing a first layer of a first barrier material on the surface of the conductive material with the sidewalls of the dielectric material remaining exposed, the first barrier material being such that, if annealed in an annealing process, the first barrier material would diffuse into the conductive material. The method further includes modifying the first barrier material on the exposed surface to form a second barrier material, the second barrier material being such that, during an annealing process, the second barrier material does not diffuse into the conductive material and depositing a second layer of the first barrier material along the sidewalls of the opening. Still further, the method includes annealing the semiconductor substrate. Integrated circuits fabricated in accordance with the foregoing method are also disclosed.

Abstract translation: 一种用于制造集成电路的方法包括提供覆盖半导体衬底的导电材料和覆盖导电材料的电介质材料，其中开口暴露导电材料的表面和电介质材料的侧壁，并选择性地沉积第一层 导电材料的表面上的阻挡材料，其中电介质材料的侧壁保持暴露，第一阻挡材料使得如果在退火过程中退火，则第一阻挡材料将扩散到导电材料中。 该方法还包括修改暴露表面上的第一阻挡材料以形成第二阻挡材料，第二阻挡材料使得在退火过程期间，第二阻挡材料不会扩散到导电材料中并沉积第二阻挡层 沿着开口的侧壁的第一阻挡材料。 此外，该方法包括退火半导体衬底。 还公开了根据前述方法制造的集成电路。

公开(公告)号：US08753975B1

公开(公告)日：2014-06-17

申请号：US13757288

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L21/4763

CPC classification number: H01L21/76873 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a trench/via in a layer of insulating material, forming a first layer comprised of silicon or germanium on the insulating material in the trench/via, forming a copper-based seed layer on the first layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based nitride layer positioned between the copper-based conductive structure and the layer of insulating material, wherein the copper-based nitride layer contacts both of the copper-based conductive structure and the layer of insulating material.

Abstract translation: 一种方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中的绝缘材料上形成由硅或锗构成的第一层，在第一层上形成铜基种子层，至少转化为 铜基种子层的一部分成为铜基氮化物层，在铜基氮化物层上沉积大量铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺以除去过量的 位于沟槽/通孔外部的材料，从而限定铜基导电结构。 一种器件包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和绝缘材料层之间的铜基氮化物层，其中 铜基氮化物层接触铜基导电结构和绝缘材料层。

公开(公告)号：USRE49820E1

公开(公告)日：2024-01-30

申请号：US16558106

申请日：2019-08-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Larry Zhao ,  Ming He ,  Xunyuan Zhang ,  Sean Xuan Lin

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

公开(公告)号：USRE47630E1

公开(公告)日：2019-10-01

申请号：US15335313

申请日：2016-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Larry Zhao ,  Ming He ,  Xunyuan Zhang ,  Sean Xuan Lin

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/48

Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

公开(公告)号：US20150255339A1

公开(公告)日：2015-09-10

申请号：US14201255

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Hoon Kim ,  Christian Witt ,  Larry Zhao

IPC: H01L21/768 ,  H01L21/306

CPC classification number: H01L21/76882 ,  H01L21/30625 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method includes forming a barrier layer in a trench/opening in an insulating material, forming a first region of a copper material above the barrier layer, forming a metal layer in the trench/opening on the first region of copper material, forming a second region of copper material on the metal layer, performing at least one CMP process to remove any materials positioned above a planarized upper surface of the layer of insulating material outside of the trench/opening so as to thereby define a structure comprised of the metal layer positioned between the first and second regions of copper material, forming a dielectric cap layer above the layer of insulating material and above the structure, and performing a metal diffusion anneal process to form a metal cap layer adjacent at least the upper surface of a conductive copper structure.

Abstract translation: 一种方法包括在绝缘材料的沟槽/开口中形成阻挡层，在阻挡层之上形成铜材料的第一区域，在铜材料的第一区域上的沟槽/开口中形成金属层，形成第二层 在金属层上的铜材料区域，执行至少一个CMP工艺以去除位于沟槽/开口外部的绝缘材料层的平坦化上表面上方的任何材料，从而限定由金属层定位的结构 在铜材料的第一和第二区域之间，在绝缘材料层之上并在结构之上形成电介质盖层，并进行金属扩散退火工艺以形成至少与导电铜结构的上表面相邻的金属盖层 。

公开(公告)号：US20140252616A1

公开(公告)日：2014-09-11

申请号：US13785934

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sean X. Lin ,  Xunyuan Zhang ,  Ming HE ,  Larry Zhao ,  John Iacoponi ,  Kunaljeet Tanwar

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76847 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/48 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench in an inter-layer dielectric formed on a semiconductor substrate is defined by a bottom and sidewalls. A copper barrier lines the trench with a copper-growth-promoting liner over the barrier. The trench has bulk copper filling it, and includes voids in the copper. The copper with voids is removed, including from the sidewalls, leaving a void-free copper portion at the bottom. Immersion in an electroless copper bath promotes upward growth of copper on top of the void-free copper portion without inward sidewall copper growth, resulting in a void-free copper fill of the trench.

Abstract translation: 在半导体衬底上形成的层间电介质中的沟槽由底部和侧壁限定。 铜屏障通过屏障上的铜生长促进衬里将沟槽排列。 沟槽有大量铜填充，并且在铜中包括空隙。 具有空隙的铜被除去，包括从侧壁，在底部留下无空隙的铜部分。 浸没在无电解铜浴中促进铜在无空隙铜部分顶部的向上生长，而不会向内侧壁铜生长，导致沟槽的无空隙铜填充。

公开(公告)号：US20150243604A1

公开(公告)日：2015-08-27

申请号：US14711280

申请日：2015-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Larry Zhao

IPC: H01L23/532 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L23/53295 ,  H01L23/535 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed herein includes forming an etch stop layer above recessed sidewall spacers and a recessed replacement gate structure and, with the etch stop layer in position, forming a self-aligned contact that is conductively coupled to the source/drain region after forming the self-aligned contact. A device disclosed herein includes an etch stop layer that is positioned above a recessed replacement gate structure and recessed sidewall spacers, wherein the etch stop layer defines an etch stop recess that contains a layer of insulating material positioned therein. The device further includes a self-aligned contact.

Abstract translation: 本文公开的一种方法包括在凹陷的侧壁间隔物和凹入的替换栅极结构上方形成蚀刻停止层，并且将蚀刻停止层置于适当位置，形成在形成自身之后与源/漏区导电耦合的自对准接触 联系人。 本文公开的装置包括位于凹入的替代栅极结构和凹陷的侧壁间隔物之上的蚀刻停止层，其中蚀刻停止层限定了包含定位在其中的绝缘材料层的蚀刻停止凹部。 该装置还包括自对准接触件。

公开(公告)号：US09070711B2

公开(公告)日：2015-06-30

申请号：US13957991

申请日：2013-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Larry Zhao

IPC: H01L29/66 ,  H01L29/51

CPC classification number: H01L23/53295 ,  H01L23/535 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed herein includes forming an etch stop layer above recessed sidewall spacers and a recessed replacement gate structure and, with the etch stop layer in position, forming a self-aligned contact that is conductively coupled to the source/drain region after forming the self-aligned contact. A device disclosed herein includes an etch stop layer that is positioned above a recessed replacement gate structure and recessed sidewall spacers, wherein the etch stop layer defines an etch stop recess that contains a layer of insulating material positioned therein. The device further includes a self-aligned contact.

Abstract translation: 本文公开的一种方法包括在凹陷的侧壁间隔物和凹入的替换栅极结构上方形成蚀刻停止层，并且将蚀刻停止层置于适当位置，形成在形成自身之后与源/漏区导电耦合的自对准接触 联系人。 本文公开的装置包括位于凹入的替代栅极结构和凹陷的侧壁间隔物之上的蚀刻停止层，其中蚀刻停止层限定了包含定位在其中的绝缘材料层的蚀刻停止凹部。 该装置还包括自对准接触件。

公开(公告)号：US08907483B2

公开(公告)日：2014-12-09

申请号：US13648433

申请日：2012-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Larry Zhao ,  Ming He ,  Xunyuan Zhang ,  Sean Xuan Lin

IPC: H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An approach for forming a semiconductor device is provided. In general, the device is formed by providing a metal layer, a cap layer over the metal layer, and an ultra low k layer over the cap layer. A via is then formed through the ultra low k layer and the cap layer. Once the via is formed, a barrier layer (e.g., cobalt (Co), tantalum (Ta), cobalt-tungsten-phosphide (CoWP), or other metal capable of acting as a copper (CU) diffusion barrier) is selectively applied to a bottom surface of the via. A liner layer (e.g., manganese (MN) or aluminum (AL)) is then applied to a set of sidewalls of the via. The via may then be filled with a subsequent metal layer (with or without a seed layer), and the device may the then be further processed (e.g., annealed).

Abstract translation: 提供了一种用于形成半导体器件的方法。 通常，通过在金属层上设置金属层，覆盖层和覆盖层上的超低k层来形成器件。 然后通过超低k层和盖层形成通孔。 一旦形成通孔，就可以选择性地将阻挡层（例如钴（Co），钽（Ta），钴 - 钨 - 磷化物（CoWP）或其它能够用作铜（CU）扩散阻挡层的金属） 通孔的底面。 然后将衬垫层（例如锰（MN）或铝（AL））施加到通孔的一组侧壁。 然后可以用随后的金属层（具有或不具有种子层）填充通孔，然后可以进一步处理（例如，退火）该器件。

公开(公告)号：US08859419B2

公开(公告)日：2014-10-14

申请号：US13757338

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L23/58 ,  H01L29/04 ,  H01L31/036 ,  H01L29/06 ,  H01L31/0352 ,  H01L23/22 ,  H01L23/24 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in the trench/via, forming a copper-based seed layer on the barrier layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device disclosed herein includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based silicon or germanium nitride layer positioned between the copper-based conductive structure and the layer of insulating material.

Abstract translation: 本文公开的一种说明性方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中形成阻挡层，在阻挡层上形成铜基种子层，将至少一部分铜基 种子层形成铜基氮化物层，在铜基氮化物层上沉积大块铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺，以去除位于沟槽之外的多余材料 / via，从而限定铜基导电结构。 本文公开的装置包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和层之间的铜基硅或氮化锗层 的绝缘材料。